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@@ -115,6 +115,7 @@ module RegMap #(
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output reg [CMD_REG_WIDTH/2-1:0] SpiTxRxEnSetReg_o,
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output reg [CMD_REG_WIDTH/2-1:0] SpiTxRxEnClrReg_o,
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output [CMD_REG_WIDTH-1:0] GPIOAReg_o,
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+ output reg [CMD_REG_WIDTH/2-1:0] LdMaskReg_o,
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output [CMD_REG_WIDTH/2-1:0] AnsDataReg_o,
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@@ -233,6 +234,9 @@ module RegMap #(
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localparam GPIO_CTRL_ADDR = 12'hFF0;
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localparam GPIO_CTRL_ADDR_S = 12'hFF2;
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+ /* LD Mask and LD Register */
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+ localparam LD_REG_ADDR = 12'hFF4;
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+ localparam LD_MASK_ADDR = 12'hFF8;
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//================================================================================
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// CODING
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@@ -292,6 +296,7 @@ module RegMap #(
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spiTxRxEnReg <= 0;
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SpiTxRxEnSetReg_o <= 0;
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SpiTxRxEnClrReg_o <= 0;
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+ LdMaskReg_o <= 0;
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GPIOAReg <= 0;
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GPIOARegS <= 0;
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ledReg <= 0;
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@@ -436,6 +441,9 @@ module RegMap #(
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SPI_TX_RX_EN_CLR : begin
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spiTxRxEnReg <= (spiTxRxEnReg) & (~Data_i);
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end
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+ LD_MASK_ADDR : begin
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+ LdMaskReg_o <= Data_i;
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+ end
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GPIO_CTRL_ADDR : begin
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GPIOAReg <= Data_i;
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end
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@@ -581,6 +589,9 @@ module RegMap #(
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SPI_TX_RX_EN_CLR : begin
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spiTxRxEnReg[15:8] <= (spiTxRxEnReg[15:8]) & (~Data_i[15:8]);
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end
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+ LD_MASK_ADDR : begin
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+ LdMaskReg_o[15:8] <= Data_i[15:8];
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+ end
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GPIO_CTRL_ADDR : begin
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GPIOAReg[15:8] <= Data_i[15:8];
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end
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@@ -726,6 +737,9 @@ module RegMap #(
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SPI_TX_RX_EN_CLR : begin
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spiTxRxEnReg[7:0] <= (spiTxRxEnReg[7:0]) & (~Data_i[7:0]);
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end
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+ LD_MASK_ADDR : begin
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+ LdMaskReg_o[7:0] <= Data_i[7:0];
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+ end
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GPIO_CTRL_ADDR : begin
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GPIOAReg[7:0] <= Data_i[7:0];
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end
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@@ -921,6 +935,12 @@ module RegMap #(
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SPI_TX_RX_EN_CLR : begin
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ansReg = SpiTxRxEnClrReg_o;
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end
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+ LD_MASK_ADDR : begin
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+ ansReg = LdMaskReg_o;
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+ end
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+ LD_REG_ADDR : begin
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+ ansReg = {9'd0,LdReg_i};
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+ end
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SPI_TX_RX_FLAGS : begin
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ansReg = {1'h0, RxFifoCtrlReg6_i[2], RxFifoCtrlReg5_i[2], RxFifoCtrlReg4_i[2], RxFifoCtrlReg3_i[2], RxFifoCtrlReg2_i[2], RxFifoCtrlReg1_i[2], RxFifoCtrlReg0_i[2], 1'h0, TxFifoCtrlReg6_i[2], TxFifoCtrlReg5_i[2], TxFifoCtrlReg4_i[2], TxFifoCtrlReg3_i[2], TxFifoCtrlReg2_i[2], TxFifoCtrlReg1_i[2], TxFifoCtrlReg0_i[2]};
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end
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