Timing issues

SRAM/QuadSPIm.v

@@ -28,10 +28,10 @@ module QuadSPIm(
 //  REG/WIRE
 //================================================================================
 reg startFlag;
-reg startR;
 reg [31:0] trCnt;
+
 reg valReg;
-reg valToRxFifo1;
+reg lineBusy;
 reg [5:0] ssCnt;
 reg Ss;
 reg SSr;
@@ -50,35 +50,38 @@ wire SsPol = SELST_i ? Ss : ~Ss;
 //================================================================================
 
 assign Ss_o = Ss; 
-assign Val_o = (trCnt < 1 ) ?valToRxFifo1:valReg;
+assign Val_o = (trCnt < 1 ) ?!lineBusy:valReg;
 //================================================================================
 //  CODING
 //================================================================================	
 
-always @(posedge Clk_i) begin 
-    startR <= Start_i;
-end
 
 always @(*) begin 
-    if (Rst_i) begin 
-        valToRxFifo1 = 1'b0;
+    if (SELST_i) begin 
+        if (!Ss) begin 
+            lineBusy = 1'b1;
+        end
+        else begin 
+            lineBusy = 1'b0;
+        end
     end
     else begin 
-        if (Start_i && !startR) begin 
-            valToRxFifo1 = 1'b1;
+        if (Ss) begin 
+            lineBusy = 1'b1;
         end
         else begin 
-            valToRxFifo1 = 1'b0;
+            lineBusy = 1'b0;
         end
     end
 end
 
+
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
         trCnt <= 1'b0;
     end
     else begin 
-        if ( (ssNum + LEAD_i + LAG_i)-1) begin 
+        if ( ssCnt == (ssNum + LEAD_i + LAG_i)-1) begin 
             trCnt <= trCnt + 1'b1;
         end
     end
@@ -439,7 +442,7 @@ always @(*) begin
         startFlag = 1'b0;
     end
     else begin 
-        if (Start_i&& !stopFlag) begin 
+        if (Start_i&& !stopFlag && SPIdata != 0) begin 
             startFlag = 1'b1;
         end
         else begin 

sources_1/new/DspSmc/SmcRx.v

@@ -62,7 +62,7 @@ module	SmcRx
 	assign	Addr_o	=	addrReg;
 	assign	Val_o	=	valReg;
 	
-	assign	SmcD_i	=	(!SmcAre_i)?	outDataReg:15'bz;
+	assign	SmcD_i	=	(!SmcAre_i)?	outDataReg:16'bz;
 //================================================================================
 //  CODING
 	

sources_1/new/MMCM/ClkGen.v

@@ -8,7 +8,7 @@ module ClkGen (
 reg [16:0] cnt;
 
 reg clk;
-
+wire clk_o;
 
 
 always @(posedge Clk_i) begin 
@@ -25,8 +25,13 @@ always @(posedge Clk_i) begin
     end
 end
 
-assign Clk_o = (cnt < ClkDiv_i/2+1) ? 1 : 0;
+assign clk_o = (cnt < ClkDiv_i/2+1) ? 1 : 0;
+
 
+BUFG BUFG_inst (
+   .O(Clk_o), // 1-bit output: Clock output
+   .I(clk_o)  // 1-bit input: Clock input
+);
 
 
 

sources_1/new/MMCM/ClkOutMMCM.v

@@ -9,7 +9,7 @@ input clk4out,
 input clk5out,
 input clk6out, 
 
-output reg [6:0] clkOutMMCM
+output reg  clkOutMMCM
 
 );
 

sources_1/new/MMCM/MmcmWrapper.v

@@ -16,7 +16,9 @@ module MmcmWrapper
 
 
 
-	output 	[SpiNum-1:0]	SpiClk_o
+	output 	[SpiNum-1:0]	SpiClk_o,
+   output	Clk100_o,
+   output   Clk40_o
 );
 //================================================================================
 //	REG/WIRE
@@ -86,6 +88,9 @@ wire [SpiNum-1:0] spiClk;
    assign SpiClk_o[5] = spiClk[5];
    assign SpiClk_o[6] = spiClk[6];
 
+   assign Clk100_o = clk0out;
+   assign Clk40_o = clk5out;
+
 
 
 //================================================================================
@@ -101,41 +106,41 @@ wire [SpiNum-1:0] spiClk;
 
    
 
-genvar i;
-
-generate
-   for (i=0; i < SpiNum; i = i +1) begin : ClkGen
-      ClkGen ClkGen_inst (
-         .Clk_i(clk1out),
-         .ClkDiv_i(clkDiv[i]),
-         .Rst_i(Rst_i),
-         .Clk_o(clkMan[i])
-      );
-
-      clkOutMMCM clkOutMMCM_inst (
-         .Rst_i(Rst_i),
-         .clkNum(clkNum[i]),
-         .clk0out(clk0out),
-         .clk1out(clk1out),
-         .clk2out(clk2out),
-         .clk3out(clk3out),
-         .clk4out(clk4out),
-         .clk5out(clk5out),
-         .clk6out(clk6out),
-         .clkOutMMCM(clkOutMMCM[i])
-      );
-
-      ClkCh ClkCh_inst (
-         .Rst_i(Rst_i),
-         .clkCh(clkCh[i]),
-         .clkOutMMCM(clkOutMMCM[i]),
-         .clkMan(clkMan[i]),
-         .SpiClk_o(spiClk[i])
-      );
-   end
-
-
-endgenerate
+// genvar i;
+
+// generate
+//    for (i=0; i < SpiNum; i = i +1) begin : ClkGen
+//       ClkGen ClkGen_inst (
+//          .Clk_i(clk1out),
+//          .ClkDiv_i(clkDiv[i]),
+//          .Rst_i(Rst_i),
+//          .Clk_o(clkMan[i])
+//       );
+
+//       clkOutMMCM clkOutMMCM_inst (
+//          .Rst_i(Rst_i),
+//          .clkNum(clkNum[i]),
+//          .clk0out(clk0out),
+//          .clk1out(clk1out),
+//          .clk2out(clk2out),
+//          .clk3out(clk3out),
+//          .clk4out(clk4out),
+//          .clk5out(clk5out),
+//          .clk6out(clk6out),
+//          .clkOutMMCM(clkOutMMCM[i])
+//       );
+
+//       ClkCh ClkCh_inst (
+//          .Rst_i(Rst_i),
+//          .clkCh(clkCh[i]),
+//          .clkOutMMCM(clkOutMMCM[i]),
+//          .clkMan(clkMan[i]),
+//          .SpiClk_o(spiClk[i])
+//       );
+//    end
+
+
+// endgenerate
 
 
 

sources_1/new/S5443_3Top.v

@@ -206,7 +206,8 @@ wire [0:31] dataToRxFifoQ [SpiNum-1:0];
 wire [0:31] dataFromRxFifo [SpiNum-1:0];
 
 wire [CmdRegWidth/2-1:0] muxedData;
-
+wire Clk100_o;
+wire Clk40_o;
 
 
 
@@ -413,13 +414,13 @@ assign Sck[4] = (spiMode)? SckQ[4]:SckR[4];
 assign Sck[5] = (spiMode)? SckQ[5]:SckR[5];
 assign Sck[6] = (spiMode)? SckQ[6]:SckR[6];
 
-assign Mosi0[0] = (spiMode)? Mosi0Q[0]:valReg[0];
-assign Mosi0[1] = (spiMode)? Mosi0Q[1]:valReg[1];
-assign Mosi0[2] = (spiMode)? Mosi0Q[2]:valReg[2];
-assign Mosi0[3] = (spiMode)? Mosi0Q[3]:valReg[3];
-assign Mosi0[4] = (spiMode)? Mosi0Q[4]:valReg[4];
-assign Mosi0[5] = (spiMode)? Mosi0Q[5]:valReg[5];
-assign Mosi0[6] = (spiMode)? Mosi0Q[6]:valReg[6];
+assign Mosi0[0] = (spiMode)? Mosi0Q[0]:Mosi0R[0];
+assign Mosi0[1] = (spiMode)? Mosi0Q[1]:Mosi0R[1];
+assign Mosi0[2] = (spiMode)? Mosi0Q[2]:Mosi0R[2];
+assign Mosi0[3] = (spiMode)? Mosi0Q[3]:Mosi0R[3];
+assign Mosi0[4] = (spiMode)? Mosi0Q[4]:Mosi0R[4];
+assign Mosi0[5] = (spiMode)? Mosi0Q[5]:Mosi0R[5];
+assign Mosi0[6] = (spiMode)? Mosi0Q[6]:Mosi0R[6];
 
 assign valToTxFifoRead[0] = (spiMode)? valToTxQ[0]:valToTxR[0];
 assign valToTxFifoRead[1] = (spiMode)? valToTxQ[1]:valToTxR[1];
@@ -608,7 +609,9 @@ MmcmWrapper MainMmcm
     .BaudRate4_i(baudRate[4]),
     .BaudRate5_i(baudRate[5]),
     .BaudRate6_i(baudRate[6]),
-	.SpiClk_o	(spiClkBus)
+	.SpiClk_o	(spiClkBus),
+    .Clk100_o   (Clk100_o),
+    .Clk40_o    (Clk40_o)
 );
 
 
@@ -629,7 +632,7 @@ generate
 		DataFifoWrapper DataFifoWrapper
 		(
 			.WrClk_i	(gclk),
-			.RdClk_i	(spiClkBus[i]),
+			.RdClk_i	(Clk40_o),
 			// .Rst_i		(spiSyncRst[i] | FifoRxRst[i]),
 			.FifoRxRst_i    (fifoRxRst[i]),
             .FifoTxRst_i    (fifoTxRst[i]),
@@ -651,13 +654,13 @@ generate
 
 
         SPIm SPIm_inst (
-            .Clk_i(spiClkBus[i]),
+            .Clk_i(Clk40_o),
             .Start_i(ten[i]),
             .Rst_i(initRst| spiMode[i]),
             .SPIdata(toSpiData[i]),
             .Sck_o(SckR[i]),
             .Ss_o(SsR[i]),
-            .Mosi0_o(valReg[i]),
+            .Mosi0_o(Mosi0R[i]),
             .WidthSel_i(widthSel[i]),
             .PulsePol_i(CPOL[i]),
             .CPHA_i(CPHA[i]),
@@ -677,11 +680,11 @@ generate
         );
 
         SPIs SPIs_inst (
-            .Clk_i(spiClkBus[i]),
+            .Clk_i(Clk40_o),
             .Rst_i(initRst|SpiRst_o[i]| spiMode[i]),
             .Sck_i(SckR[i]),
             .Ss_i(SsR[i]),
-            .Mosi0_i(valReg[i]),
+            .Mosi0_i(Mosi0R[i]),
             .WidthSel_i(widthSel[i]),
             .SELST_i(selSt[i]),
             .DataToRxFifo_o(dataToRxFifoR[i]),
@@ -690,7 +693,7 @@ generate
 
 
         QuadSPIm QuadSPIm_inst (
-            .Clk_i(spiClkBus[i]),
+            .Clk_i(Clk40_o),
             .Start_i(ten[i]),
             .Rst_i(initRst| !spiMode[i]),
 			.SpiDataVal_i	(toSpiVal),
@@ -713,11 +716,11 @@ generate
             .Val_o(valToTxQ[i])
         );
         QuadSPIs QuadSPIs_inst (
-            .Clk_i(spiClkBus[i]),
+            .Clk_i(Clk40_o),
             .Rst_i(initRst|SpiRst_o[i]| !spiMode[i]),
             .Sck_i(SckQ[i]),
             .Ss_i(SsQ[i]),
-            .Mosi0_i(Mosi0[i]),
+            .Mosi0_i(Mosi0Q[i]),
             .Mosi1_i(Mosi1[i]),
             .Mosi2_i(Mosi2[i]),
             .Mosi3_i(Mosi3[i]),

sources_1/new/SpiR/SPIm.v

@@ -29,7 +29,7 @@ reg startFlag;
 reg startR;
 reg [31:0] trCnt;
 reg valReg;
-reg valToRxFifo1;
+reg lineBusy;
 reg [5:0] ssCnt;
 reg Ss;
 reg SSr;
@@ -51,24 +51,26 @@ assign Ss_o = SsPol;
 
 
 
-assign Val_o = (trCnt < 1 ) ?valToRxFifo1:valReg;
+assign Val_o = (trCnt < 1 ) ?!lineBusy:valReg;
 //================================================================================
 //	CODING
 //================================================================================
-always @(posedge Clk_i) begin 
-    startR <= Start_i;
-end
 
 always @(*) begin 
-    if (Rst_i) begin 
-        valToRxFifo1 = 1'b0;
+    if (SELST_i) begin 
+        if (!Ss) begin 
+            lineBusy = 1'b1;
+        end
+        else begin 
+            lineBusy = 1'b0;
+        end
     end
     else begin 
-        if (Start_i && !startR) begin 
-            valToRxFifo1 = 1'b1;
+        if (Ss) begin 
+            lineBusy = 1'b1;
         end
         else begin 
-            valToRxFifo1 = 1'b0;
+            lineBusy = 1'b0;
         end
     end
 end
@@ -78,7 +80,7 @@ always @(posedge Clk_i) begin
         trCnt <= 1'b0;
     end
     else begin 
-        if ( (ssNum + LEAD_i + LAG_i)-1) begin 
+        if ( ssCnt == (ssNum + LEAD_i + LAG_i)-1) begin 
             trCnt <= trCnt + 1'b1;
         end
     end
@@ -377,7 +379,7 @@ always @(*) begin
         startFlag = 1'b0;
     end
     else begin 
-        if (Start_i && !stopFlag) begin 
+        if (Start_i && !stopFlag && SPIdata != 0 ) begin 
             startFlag = 1'b1;
         end
         else begin 

sources_1/new/SpiR/SPIm_tb.v

@@ -118,8 +118,8 @@ module tb_SPIm;
         Rst_i = 1;
         Start_i = 0;
         CPHA_i = 0;
-        SPIdata =  {1'h0, 7'h2a, 8'haa,8'h00,8'haa}; // Example SPI data
 		SpiDataVal_i = 0;
+        SPIdata = 32'h00000000;
         SELST_i = 1;//0:High, 1:Low
         WidthSel_i = 3; // Full 32-bit width
         LAG_i = 0;
@@ -131,6 +131,8 @@ module tb_SPIm;
         // Reset the system
         #(CLK_PERIOD*10) Rst_i = 0;
         #(CLK_PERIOD*2) Start_i = 1; // Start SPI transaction
+        #(CLK_PERIOD*10)SPIdata =  {1'h0, 7'h2a, 8'haa,8'h00,8'haa};
+        //    #(CLK_PERIOD*10)SPIdata =  32'haa;
 
     
         #(CLK_PERIOD*100);