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Исправлены ошибки при симуляции с параметром SpiNum = 1.

Anatoliy Chigirinskiy hace 1 año
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6a98d5b755
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a198f647dd
Se han modificado 2 ficheros con 15 adiciones y 91 borrados
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  1. 12 37
      sources_1/new/MMCM/MmcmWrapper.v
  2. 3 54
      sources_1/new/S5443_3Top.v

+ 12 - 37
sources_1/new/MMCM/MmcmWrapper.v
Ver fichero 

@@ -49,15 +49,7 @@ wire [SpiNum-1:0] spiClk;
 
 
 //================================================================================
 
 //	ASSIGNMENTS
 
-//================================================================================
 
-	// assign SpiClk_o[0]	=	clk1out;
 
-   // assign SpiClk_o[1]	=	clk2out;
 
-   // assign SpiClk_o[2]	=	clk3out;
 
-   // assign SpiClk_o[3]	=	clk4out;
 
-   // assign SpiClk_o[4]	=	clk5out;
 
-   // assign SpiClk_o[5]	=	clk6out;
 
-   // assign SpiClk_o[6]	=	clk7out;
 
-
 
+//===============================================================================
 
    assign clkNum[0] = BaudRate0_i[7:5];
 
    assign clkNum[1] = BaudRate1_i[7:5];
 
    assign clkNum[2] = BaudRate2_i[7:5];
 
@@ -82,19 +74,18 @@ wire [SpiNum-1:0] spiClk;
 
    assign clkCh[5] = BaudRate5_i[4];
 
    assign clkCh[6] = BaudRate6_i[4];
 
 
-   assign SpiClk_o[0] = spiClk[0];
 
-   assign SpiClk_o[1] = spiClk[1];
 
-   assign SpiClk_o[2] = spiClk[2];
 
-   assign SpiClk_o[3] = spiClk[3];
 
-   assign SpiClk_o[4] = spiClk[4];
 
-   assign SpiClk_o[5] = spiClk[5];
 
-   assign SpiClk_o[6] = spiClk[6];
 
+   // assign SpiClk_o[0] = spiClk[0];
 
+   // assign SpiClk_o[1] = spiClk[1];
 
+   // assign SpiClk_o[2] = spiClk[2];
 
+   // assign SpiClk_o[3] = spiClk[3];
 
+   // assign SpiClk_o[4] = spiClk[4];
 
+   // assign SpiClk_o[5] = spiClk[5];
 
+   // assign SpiClk_o[6] = spiClk[6];
 
 
+   assign SpiClk_o = spiClk; 
    assign Clk100_o = clk0out;
 
    assign Clk80_o = clk1out;
 
 
-
 
-
 
    //================================================================================
 
    //	LOCALPARAMS
 
    //================================================================================
 
@@ -102,13 +93,9 @@ wire [SpiNum-1:0] spiClk;
 
    
    //================================================================================
 
    //	CODING
 
-   //================================================================================
 
-   
-   
-   
-      
+   //================================================================================   
    genvar i;
 
-   
+
 
    generate
 
       for (i=0; i < SpiNum; i = i +1) begin : ClkGen
 
          ClkGen ClkGen_inst (
 
@@ -128,7 +115,6 @@ wire [SpiNum-1:0] spiClk;
 
             .ClkDiv_o(clkDivSync[i])
 
 
          );
 
-         
 
          clkOutMMCM clkOutMMCM_inst (
 
             .Rst_i(Rst_i),
 
@@ -151,14 +137,8 @@ wire [SpiNum-1:0] spiClk;
 
             .SpiClk_o(spiClk[i])
 
          );
 
       end
 
-   
-   
    endgenerate
 
    
-   
-   
-   
-   
    ClkDiv ClkDiv_inst
 
     (
 
      // Clock out ports
 
@@ -167,7 +147,7 @@ wire [SpiNum-1:0] spiClk;
 
      .clk_out3(clk2out),     // 70 MHz
 
      .clk_out4(clk3out),     // 60MHz
 
      .clk_out5(clk4out),     // 50MHz
 
-   //   .clk_out6(clk5out),     // 40MHz
 
+     .clk_out6(clk5out),     // 40MHz
 
      .clk_out7(clk6out),     // 30MHz 
      // Status and control signals
 
      .reset(Rst_i), // input reset
 
@@ -175,9 +155,4 @@ wire [SpiNum-1:0] spiClk;
 
     // Clock in ports
 
      .clk_in1(Clk_i));      // input clk_in1
 
    
-   
-      
-   
-   
-   
    endmodule

+ 3 - 54
sources_1/new/S5443_3Top.v
Ver fichero 

@@ -25,7 +25,7 @@ module S5443_3Top
 
     parameter CmdRegWidth = 32,
 
     parameter AddrRegWidth = 12,
 
     parameter STAGES = 3,
 
-    parameter SpiNum = 7
 
+    parameter SpiNum = 1
 
 
 )
 
 (
 
@@ -305,13 +305,6 @@ module S5443_3Top
 
     assign Mosi1_io[6] =(SpiDir_o[6])?mosi1[6]:1'bz;
 
     assign Mosi2_o = mosi2;
 
     assign Mosi3_o = mosi3;
 
-    // assign Ss_o[0] = (assel[0])? ((chipSelFpga[0])? ssMuxed[0]:~ssMuxed[0]):chipSelFpga[0];
 
-    // assign Ss_o[1] = (assel[1])? ((chipSelFpga[1])? ssMuxed[1]:~ssMuxed[1]):chipSelFpga[1];
 
-    // assign Ss_o[2] = (assel[2])? ((chipSelFpga[2])? ssMuxed[2]:~ssMuxed[2]):chipSelFpga[2];
 
-    // assign Ss_o[3] = (assel[3])? ((chipSelFpga[3])? ssMuxed[3]:~ssMuxed[3]):chipSelFpga[3];
 
-    // assign Ss_o[4] = (assel[4])? ((chipSelFpga[4])? ssMuxed[4]:~ssMuxed[4]):chipSelFpga[4];
 
-    // assign Ss_o[5] = (assel[5])? ((chipSelFpga[5])? ssMuxed[5]:~ssMuxed[5]):chipSelFpga[5];
 
-    // assign Ss_o[6] = (assel[6])? ((chipSelFpga[6])? ssMuxed[6]:~ssMuxed[6]):chipSelFpga[6];
 
 
     assign Ss_o[0] = (assel[0]) ? (chipSelFpga[0] ? ssMuxed[0] : 1'b1) : chipSelFpga[0];
 
     assign Ss_o[1] = (assel[1]) ? (chipSelFpga[1] ? ssMuxed[1] : 1'b1) : chipSelFpga[1];
 
@@ -321,27 +314,6 @@ module S5443_3Top
 
     assign Ss_o[5] = (assel[5]) ? (chipSelFpga[5] ? ssMuxed[5] : 1'b1) : chipSelFpga[5];
 
     assign Ss_o[6] = (assel[6]) ? (chipSelFpga[6] ? ssMuxed[6] : 1'b1) : chipSelFpga[6];
 
 
-
 
-
 
-    // assign SsFlash_o[0] = (assel[0])?(chipSelFlash[0]? ssMuxed[0]:~ssMuxed[0]):chipSelFlash[0];
 
-    // assign SsFlash_o[1] = (assel[1])?(chipSelFlash[1]? ssMuxed[1]:~ssMuxed[1]):chipSelFlash[1];
 
-    // assign SsFlash_o[2] = (assel[2])?(chipSelFlash[2]? ssMuxed[2]:~ssMuxed[2]):chipSelFlash[2];
 
-    // assign SsFlash_o[3] = (assel[3])?(chipSelFlash[3]? ssMuxed[3]:~ssMuxed[3]):chipSelFlash[3];
 
-    // assign SsFlash_o[4] = (assel[4])?(chipSelFlash[4]? ssMuxed[4]:~ssMuxed[4]):chipSelFlash[4];
 
-    // assign SsFlash_o[5] = (assel[5])?(chipSelFlash[5]? ssMuxed[5]:~ssMuxed[5]):chipSelFlash[5];
 
-    // assign SsFlash_o[6] = (assel[6])?(chipSelFlash[6]? ssMuxed[6]:~ssMuxed[6]):chipSelFlash[6];
 
-
 
-    // assign SsFlash_o[0] = (assel[0]) ? ssMuxed[0] : chipSelFlash[0];
 
-    // assign SsFlash_o[1] = (assel[1]) ? ssMuxed[1] : chipSelFlash[1];
 
-    // assign SsFlash_o[2] = (assel[2]) ? ssMuxed[2] : chipSelFlash[2];
 
-    // assign SsFlash_o[3] = (assel[3]) ? ssMuxed[3] : chipSelFlash[3];
 
-    // assign SsFlash_o[4] = (assel[4]) ? ssMuxed[4] : chipSelFlash[4];
 
-    // assign SsFlash_o[5] = (assel[5]) ? ssMuxed[5] : chipSelFlash[5];
 
-    // assign SsFlash_o[6] = (assel[6]) ? ssMuxed[6] : chipSelFlash[6];
 
-
 
-
 
-
 
-
 
     assign SsFlash_o[0] = (assel[0]) ? (chipSelFlash[0] ? ssMuxed[0] : 1'b1) : chipSelFlash[0];
 
     assign SsFlash_o[1] = (assel[1]) ? (chipSelFlash[1] ? ssMuxed[1] : 1'b1) : chipSelFlash[1];
 
     assign SsFlash_o[2] = (assel[2]) ? (chipSelFlash[2] ? ssMuxed[2] : 1'b1) : chipSelFlash[2];
 
@@ -350,12 +322,8 @@ module S5443_3Top
 
     assign SsFlash_o[5] = (assel[5]) ? (chipSelFlash[5] ? ssMuxed[5] : 1'b1) : chipSelFlash[5];
 
     assign SsFlash_o[6] = (assel[6]) ? (chipSelFlash[6] ? ssMuxed[6] : 1'b1) : chipSelFlash[6];
 
 
-
 
-
 
-
 
-
 
     assign Sck_o = sckMuxed;
 
-    
+
 
     assign widthSel[0] = spi0CtrlRR[6:5];
 
     assign widthSel[1] = spi1CtrlRR[6:5];
 
     assign widthSel[2] = spi2CtrlRR[6:5];
 
@@ -371,7 +339,6 @@ module S5443_3Top
 
     assign spiEn[4] = spi4CtrlRR[0];
 
     assign spiEn[5] = spi5CtrlRR[0];
 
     assign spiEn[6] = spi6CtrlRR[0];
 
-
 
     
     assign spiMode[0] = spi0CtrlRR[7];
 
     assign spiMode[1] = spi1CtrlRR[7];
 
@@ -381,7 +348,6 @@ module S5443_3Top
 
     assign spiMode[5] = spi5CtrlRR[7];
 
     assign spiMode[6] = spi6CtrlRR[7];
 
     
-    
     assign clockPol[0] = spi0CtrlRR[2];
 
     assign clockPol[1] = spi1CtrlRR[2];
 
     assign clockPol[2] = spi2CtrlRR[2];
 
@@ -454,7 +420,6 @@ module S5443_3Top
 
     assign baudRate[5] = spi5Clk[7:0];
 
     assign baudRate[6] = spi6Clk[7:0];
 
     
-    
     assign SpiRst_o[0] = GPIOA[0];
 
     assign SpiRst_o[1] = GPIOA[1];
 
     assign SpiRst_o[2] = GPIOA[2];
 
@@ -520,7 +485,6 @@ module S5443_3Top
 
     assign wordCntTx[5] = spi5TxFifoCtrlRR[15:8];
 
     assign wordCntTx[6] = spi6TxFifoCtrlRR[15:8];
 
     
-    
     assign chipSelFpga[0] = spi0CsCtrlRR[0];
 
     assign chipSelFpga[1] = spi1CsCtrlRR[0];
 
     assign chipSelFpga[2] = spi2CsCtrlRR[0];
 
@@ -537,7 +501,6 @@ module S5443_3Top
 
     assign chipSelFlash[5] = spi5CsCtrlRR[1];
 
     assign chipSelFlash[6] = spi6CsCtrlRR[1];
 
     
-    
     assign ssMuxed[0] = (spiMode[0])? ssQ[0]:ssR[0];
 
     assign ssMuxed[1] = (spiMode[1])? ssQ[1]:ssR[1];
 
     assign ssMuxed[2] = (spiMode[2])? ssQ[2]:ssR[2];
 
@@ -554,7 +517,6 @@ module S5443_3Top
 
     assign SpiDir_o[5] = (spiMode[5])? 1'b1 : 1'b0 ;
 
     assign SpiDir_o[6] = (spiMode[6])? 1'b1 : 1'b0 ;
 
     
-    
     assign sckMuxed[0] =  (spiMode[0])?sckQ[0]:sckR[0];
 
     assign sckMuxed[1] =  (spiMode[1])?sckQ[1]:sckR[1];
 
     assign sckMuxed[2] =  (spiMode[2])?sckQ[2]:sckR[2];
 
@@ -571,14 +533,7 @@ module S5443_3Top
 
     assign mosi0[5] =  (spiMode[5])?mosi0Q[5]:mosi0R[5];
 
     assign mosi0[6] =  (spiMode[6])?mosi0Q[6]:mosi0R[6];
 
     
-    assign Mosi0_o[0] = mosi0[0];
 
-    assign Mosi0_o[1] = mosi0[1];
 
-    assign Mosi0_o[2] = mosi0[2];
 
-    assign Mosi0_o[3] = mosi0[3];
 
-    assign Mosi0_o[4] = mosi0[4];
 
-    assign Mosi0_o[5] = mosi0[5];
 
-    assign Mosi0_o[6] = mosi0[6];
 
-    
+    assign Mosi0_o = mosi0;
 
     
     assign valToTxFifoRead[0] =  (spiMode[0])?valToTxQ[0]:valToTxR[0];
 
     assign valToTxFifoRead[1] =  (spiMode[1])?valToTxQ[1]:valToTxR[1];
 
@@ -620,8 +575,6 @@ module S5443_3Top
 
     assign spi5RxFifoCtrlReg = rxFifoCtrlReg[5];
 
     assign spi6RxFifoCtrlReg = rxFifoCtrlReg[6];
 
     
-    
-    
     assign	SmcData_io	=	(!SmcAre_i && !SmcAoe_i)?muxedData:16'bz;
 
     
     //================================================================================
 
@@ -653,7 +606,6 @@ module S5443_3Top
 
        .I(Clk123_i)  // 1-bit input: Clock input
 
     );
 
     
-    
     DataMuxer DataMuxer
 
     (
 
         .Clk_i(gclk),
 
@@ -672,7 +624,6 @@ module S5443_3Top
 
     
     );
 
     
-
 
     CDC #(
 
 
         .WIDTH(CmdRegWidth),
 
@@ -768,7 +719,6 @@ module S5443_3Top
 
 
     );
 
 
-
 
     RegMap 
     #(
 
         .CmdRegWidth(32),
 
@@ -1002,5 +952,4 @@ module S5443_3Top
 
         .signal_o(rst80)
 
     );
 
     
-    
     endmodule