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@@ -10,7 +10,23 @@ module RegMap #(
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input Clk_i,
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input Rst_i,
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- input [1:0] SmcBe_i,
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+ input [1:0] SmcBe_i,
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+ input [CmdRegWidth-1:0] TxFifoCtrlReg0_i,
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+ input [CmdRegWidth-1:0] RxFifoCtrlReg0_i,
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+ input [CmdRegWidth-1:0] TxFifoCtrlReg1_i,
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+ input [CmdRegWidth-1:0] RxFifoCtrlReg1_i,
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+ input [CmdRegWidth-1:0] TxFifoCtrlReg2_i,
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+ input [CmdRegWidth-1:0] RxFifoCtrlReg2_i,
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+ input [CmdRegWidth-1:0] TxFifoCtrlReg3_i,
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+ input [CmdRegWidth-1:0] RxFifoCtrlReg3_i,
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+ input [CmdRegWidth-1:0] TxFifoCtrlReg4_i,
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+ input [CmdRegWidth-1:0] RxFifoCtrlReg4_i,
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+ input [CmdRegWidth-1:0] TxFifoCtrlReg5_i,
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+ input [CmdRegWidth-1:0] RxFifoCtrlReg5_i,
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+ input [CmdRegWidth-1:0] TxFifoCtrlReg6_i,
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+ input [CmdRegWidth-1:0] RxFifoCtrlReg6_i,
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+
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+
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output [CmdRegWidth/2-1:0] Spi0CtrlReg_o,
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@@ -244,8 +260,10 @@ localparam Spi0CtrlAddr = 12'h00;
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localparam Spi0ClkAddr = 12'h04;
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localparam Spi0CsDelayAddr = 12'h08;
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localparam Spi0CsCtrlAddr = 12'h0c;
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-localparam Spi0TxFifoCtrlAddr = 12'h10;
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-localparam Spi0RxFifoCtrlAddr = 12'h14;
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+localparam Spi0TxFifoCtrlAddrLsb = 12'h10;
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+localparam Spi0TxFifoCtrlAddrMsb = 12'h12;
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+localparam Spi0RxFifoCtrlAddrLsb = 12'h14;
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+localparam Spi0RxFifoCtrlAddrMsb = 12'h16;
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localparam Spi0TxFifo = 12'h18;
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localparam Spi0RxFifo = 12'h1c;
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@@ -253,8 +271,10 @@ localparam Spi1CtrlAddr = 12'h50;
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localparam Spi1ClkAddr = 12'h54;
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localparam Spi1CsDelayAddr = 12'h58;
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localparam Spi1CsCtrlAddr = 12'h5c;
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-localparam Spi1TxFifoCtrlAddr = 12'h60;
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-localparam Spi1RxFifoCtrlAddr = 12'h64;
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+localparam Spi1TxFifoCtrlAddrLsb = 12'h60;
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+localparam Spi1TxFifoCtrlAddrMsb = 12'h62;
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+localparam Spi1RxFifoCtrlAddrLsb = 12'h64;
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+localparam Spi1RxFifoCtrlAddrMsb = 12'h66;
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localparam Spi1TxFifo = 12'h68;
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localparam Spi1RxFifo = 12'h6c;
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@@ -262,8 +282,10 @@ localparam Spi2CtrlAddr = 12'hF0;
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localparam Spi2ClkAddr = 12'hF4;
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localparam Spi2CsDelayAddr = 12'hF8;
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localparam Spi2CsCtrlAddr = 12'hFc;
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-localparam Spi2TxFifoCtrlAddr = 12'h100;
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-localparam Spi2RxFifoCtrlAddr = 12'h104;
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+localparam Spi2TxFifoCtrlAddrLsb = 12'h100;
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+localparam Spi2TxFifoCtrlAddrMsb = 12'h102;
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+localparam Spi2RxFifoCtrlAddrLsb = 12'h104;
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+localparam Spi2RxFifoCtrlAddrMsb = 12'h106;
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localparam Spi2TxFifo = 12'h108;
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localparam Spi2RxFifo = 12'h10c;
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@@ -271,8 +293,10 @@ localparam Spi3CtrlAddr = 12'h140;
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localparam Spi3ClkAddr = 12'h144;
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localparam Spi3CsDelayAddr = 12'h148;
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localparam Spi3CsCtrlAddr = 12'h14c;
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-localparam Spi3TxFifoCtrlAddr = 12'h150;
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-localparam Spi3RxFifoCtrlAddr = 12'h154;
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+localparam Spi3TxFifoCtrlAddrLsb = 12'h150;
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+localparam Spi3TxFifoCtrlAddrMsb = 12'h152;
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+localparam Spi3RxFifoCtrlAddrLsb = 12'h154;
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+localparam Spi3RxFifoCtrlAddrMsb = 12'h156;
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localparam Spi3TxFifo = 12'h158;
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localparam Spi3RxFifo = 12'h15c;
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@@ -280,8 +304,10 @@ localparam Spi4CtrlAddr = 12'h190;
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localparam Spi4ClkAddr = 12'h194;
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localparam Spi4CsDelayAddr = 12'h198;
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localparam Spi4CsCtrlAddr = 12'h19c;
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-localparam Spi4TxFifoCtrlAddr = 12'h1a0;
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-localparam Spi4RxFifoCtrlAddr = 12'h1a4;
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+localparam Spi4TxFifoCtrlAddrLsb = 12'h1a0;
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+localparam Spi4TxFifoCtrlAddrMsb = 12'h1a2;
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+localparam Spi4RxFifoCtrlAddrLsb = 12'h1a4;
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+localparam Spi4RxFifoCtrlAddrMsb = 12'h1a6;
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localparam Spi4TxFifo = 12'h1a8;
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localparam Spi4RxFifo = 12'h1ac;
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@@ -289,8 +315,10 @@ localparam Spi5CtrlAddr = 12'h1e0;
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localparam Spi5ClkAddr = 12'h1e4;
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localparam Spi5CsDelayAddr = 12'h1e8;
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localparam Spi5CsCtrlAddr = 12'h1ec;
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-localparam Spi5TxFifoCtrlAddr = 12'h1f0;
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-localparam Spi5RxFifoCtrlAddr = 12'h1f4;
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+localparam Spi5TxFifoCtrlAddrLsb = 12'h1f0;
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+localparam Spi5TxFifoCtrlAddrMsb = 12'h1f2;
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+localparam Spi5RxFifoCtrlAddrLsb = 12'h1f4;
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+localparam Spi5RxFifoCtrlAddrMsb = 12'h1f6;
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localparam Spi5TxFifo = 12'h1f8;
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localparam Spi5RxFifo = 12'h1fc;
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@@ -298,8 +326,10 @@ localparam Spi6CtrlAddr = 12'h230;
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localparam Spi6ClkAddr = 12'h234;
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localparam Spi6CsDelayAddr = 12'h238;
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localparam Spi6CsCtrlAddr = 12'h23c;
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-localparam Spi6TxFifoCtrlAddr = 12'h240;
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-localparam Spi6RxFifoCtrlAddr = 12'h244;
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+localparam Spi6TxFifoCtrlAddrLsb = 12'h240;
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+localparam Spi6TxFifoCtrlAddrMsb = 12'h242;
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+localparam Spi6RxFifoCtrlAddrLsb = 12'h244;
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+localparam Spi6RxFifoCtrlAddrMsb = 12'h246;
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localparam Spi6TxFifo = 12'h248;
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localparam Spi6RxFifo = 12'h24c;
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@@ -399,10 +429,10 @@ always @(posedge Clk_i) begin
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Spi0CsCtrlAddr : begin
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Spi0CsCtrlReg <= Data_i;
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end
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- Spi0TxFifoCtrlAddr : begin
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+ Spi0TxFifoCtrlAddrLsb : begin
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Spi0TxFifoCtrlReg <= Data_i;
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end
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- Spi0RxFifoCtrlAddr : begin
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+ Spi0RxFifoCtrlAddrLsb : begin
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Spi0RxFifoCtrlReg <= Data_i;
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end
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Spi0TxFifo : begin
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@@ -423,10 +453,10 @@ always @(posedge Clk_i) begin
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Spi1CsCtrlAddr : begin
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Spi1CsCtrlReg <= Data_i;
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end
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- Spi1TxFifoCtrlAddr : begin
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+ Spi1TxFifoCtrlAddrLsb : begin
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Spi1TxFifoCtrlReg <= Data_i;
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end
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- Spi1RxFifoCtrlAddr : begin
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+ Spi1RxFifoCtrlAddrLsb : begin
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Spi1RxFifoCtrlReg <= Data_i;
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end
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Spi1TxFifo : begin
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@@ -447,10 +477,10 @@ always @(posedge Clk_i) begin
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Spi2CsCtrlAddr : begin
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Spi2CsCtrlReg <= Data_i;
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end
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- Spi2TxFifoCtrlAddr : begin
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+ Spi2TxFifoCtrlAddrLsb : begin
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Spi2TxFifoCtrlReg <= Data_i;
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end
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- Spi2RxFifoCtrlAddr : begin
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+ Spi2RxFifoCtrlAddrLsb : begin
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Spi2RxFifoCtrlReg <= Data_i;
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end
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Spi2TxFifo : begin
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@@ -471,10 +501,10 @@ always @(posedge Clk_i) begin
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Spi3CsCtrlAddr : begin
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Spi3CsCtrlReg <= Data_i;
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end
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- Spi3TxFifoCtrlAddr : begin
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+ Spi3TxFifoCtrlAddrLsb : begin
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Spi3TxFifoCtrlReg <= Data_i;
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end
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- Spi3RxFifoCtrlAddr : begin
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+ Spi3RxFifoCtrlAddrLsb : begin
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Spi3RxFifoCtrlReg <= Data_i;
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end
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Spi3TxFifo : begin
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@@ -495,10 +525,10 @@ always @(posedge Clk_i) begin
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Spi4CsCtrlAddr : begin
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Spi4CsCtrlReg <= Data_i;
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end
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- Spi4TxFifoCtrlAddr : begin
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+ Spi4TxFifoCtrlAddrLsb : begin
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Spi4TxFifoCtrlReg <= Data_i;
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end
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- Spi4RxFifoCtrlAddr : begin
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+ Spi4RxFifoCtrlAddrLsb : begin
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Spi4RxFifoCtrlReg <= Data_i;
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end
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Spi4TxFifo : begin
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@@ -519,10 +549,10 @@ always @(posedge Clk_i) begin
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Spi5CsCtrlAddr : begin
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Spi5CsCtrlReg <= Data_i;
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end
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- Spi5TxFifoCtrlAddr : begin
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+ Spi5TxFifoCtrlAddrLsb : begin
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Spi5TxFifoCtrlReg <= Data_i;
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end
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- Spi5RxFifoCtrlAddr : begin
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+ Spi5RxFifoCtrlAddrLsb : begin
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Spi5RxFifoCtrlReg <= Data_i;
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end
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Spi5TxFifo : begin
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@@ -543,10 +573,10 @@ always @(posedge Clk_i) begin
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Spi6CsCtrlAddr : begin
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Spi6CsCtrlReg <= Data_i;
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end
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- Spi6TxFifoCtrlAddr : begin
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+ Spi6TxFifoCtrlAddrLsb : begin
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Spi6TxFifoCtrlReg <= Data_i;
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end
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- Spi6RxFifoCtrlAddr : begin
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+ Spi6RxFifoCtrlAddrLsb : begin
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Spi6RxFifoCtrlReg <= Data_i;
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end
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Spi6TxFifo : begin
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@@ -583,10 +613,10 @@ always @(posedge Clk_i) begin
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Spi0CsCtrlAddr : begin
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Spi0CsCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi0TxFifoCtrlAddr : begin
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+ Spi0TxFifoCtrlAddrLsb : begin
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Spi0TxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi0RxFifoCtrlAddr : begin
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+ Spi0RxFifoCtrlAddrLsb : begin
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Spi0RxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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Spi0TxFifo : begin
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@@ -607,10 +637,10 @@ always @(posedge Clk_i) begin
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Spi1CsCtrlAddr : begin
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Spi1CsCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi1TxFifoCtrlAddr : begin
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+ Spi1TxFifoCtrlAddrLsb : begin
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Spi1TxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi1RxFifoCtrlAddr : begin
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+ Spi1RxFifoCtrlAddrLsb : begin
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Spi1RxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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Spi1TxFifo : begin
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@@ -631,10 +661,10 @@ always @(posedge Clk_i) begin
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Spi2CsCtrlAddr : begin
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Spi2CsCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi2TxFifoCtrlAddr : begin
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+ Spi2TxFifoCtrlAddrLsb : begin
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Spi2TxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi2RxFifoCtrlAddr : begin
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+ Spi2RxFifoCtrlAddrLsb : begin
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Spi2RxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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Spi2TxFifo : begin
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@@ -655,10 +685,10 @@ always @(posedge Clk_i) begin
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Spi3CsCtrlAddr : begin
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Spi3CsCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi3TxFifoCtrlAddr : begin
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+ Spi3TxFifoCtrlAddrLsb : begin
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Spi3TxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi3RxFifoCtrlAddr : begin
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+ Spi3RxFifoCtrlAddrLsb : begin
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Spi3RxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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Spi3TxFifo : begin
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@@ -679,10 +709,10 @@ always @(posedge Clk_i) begin
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Spi4CsCtrlAddr : begin
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Spi4CsCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi4TxFifoCtrlAddr : begin
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+ Spi4TxFifoCtrlAddrLsb : begin
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Spi4TxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi4RxFifoCtrlAddr : begin
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+ Spi4RxFifoCtrlAddrLsb : begin
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Spi4RxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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Spi4TxFifo : begin
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@@ -703,10 +733,10 @@ always @(posedge Clk_i) begin
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Spi5CsCtrlAddr : begin
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Spi5CsCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi5TxFifoCtrlAddr : begin
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+ Spi5TxFifoCtrlAddrLsb : begin
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Spi5TxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi5RxFifoCtrlAddr : begin
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+ Spi5RxFifoCtrlAddrLsb : begin
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Spi5RxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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Spi5TxFifo : begin
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@@ -727,10 +757,10 @@ always @(posedge Clk_i) begin
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Spi6CsCtrlAddr : begin
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Spi6CsCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi6TxFifoCtrlAddr : begin
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+ Spi6TxFifoCtrlAddrLsb : begin
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Spi6TxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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- Spi6RxFifoCtrlAddr : begin
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+ Spi6RxFifoCtrlAddrLsb : begin
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Spi6RxFifoCtrlReg[15:8] <= Data_i[15:8];
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end
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Spi6TxFifo : begin
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@@ -767,10 +797,10 @@ always @(posedge Clk_i) begin
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Spi0CsCtrlAddr : begin
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Spi0CsCtrlReg[7:0] <= Data_i[7:0];
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end
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- Spi0TxFifoCtrlAddr : begin
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+ Spi0TxFifoCtrlAddrLsb : begin
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Spi0TxFifoCtrlReg[7:0] <= Data_i[7:0];
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end
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- Spi0RxFifoCtrlAddr : begin
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+ Spi0RxFifoCtrlAddrLsb : begin
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Spi0RxFifoCtrlReg[7:0] <= Data_i[7:0];
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end
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Spi0TxFifo : begin
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@@ -791,10 +821,10 @@ always @(posedge Clk_i) begin
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Spi1CsCtrlAddr : begin
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Spi1CsCtrlReg[7:0] <= Data_i[7:0];
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end
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- Spi1TxFifoCtrlAddr : begin
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+ Spi1TxFifoCtrlAddrLsb : begin
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Spi1TxFifoCtrlReg[7:0] <= Data_i[7:0];
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end
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- Spi1RxFifoCtrlAddr : begin
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+ Spi1RxFifoCtrlAddrLsb : begin
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Spi1RxFifoCtrlReg[7:0] <= Data_i[7:0];
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end
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Spi1TxFifo : begin
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@@ -815,10 +845,10 @@ always @(posedge Clk_i) begin
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Spi2CsCtrlAddr : begin
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Spi2CsCtrlReg[7:0] <= Data_i[7:0];
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end
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- Spi2TxFifoCtrlAddr : begin
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+ Spi2TxFifoCtrlAddrLsb : begin
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Spi2TxFifoCtrlReg[7:0] <= Data_i[7:0];
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end
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- Spi2RxFifoCtrlAddr : begin
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+ Spi2RxFifoCtrlAddrLsb : begin
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Spi2RxFifoCtrlReg[7:0] <= Data_i[7:0];
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end
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Spi2TxFifo : begin
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@@ -839,10 +869,10 @@ always @(posedge Clk_i) begin
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Spi3CsCtrlAddr : begin
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Spi3CsCtrlReg[7:0] <= Data_i[7:0];
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end
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- Spi3TxFifoCtrlAddr : begin
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+ Spi3TxFifoCtrlAddrLsb : begin
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Spi3TxFifoCtrlReg[7:0] <= Data_i[7:0];
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end
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- Spi3RxFifoCtrlAddr : begin
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+ Spi3RxFifoCtrlAddrLsb : begin
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Spi3RxFifoCtrlReg[7:0] <= Data_i[7:0];
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|
end
|
|
|
Spi3TxFifo : begin
|
|
|
@@ -863,10 +893,10 @@ always @(posedge Clk_i) begin
|
|
|
Spi4CsCtrlAddr : begin
|
|
|
Spi4CsCtrlReg[7:0] <= Data_i[7:0];
|
|
|
end
|
|
|
- Spi4TxFifoCtrlAddr : begin
|
|
|
+ Spi4TxFifoCtrlAddrLsb : begin
|
|
|
Spi4TxFifoCtrlReg[7:0] <= Data_i[7:0];
|
|
|
end
|
|
|
- Spi4RxFifoCtrlAddr : begin
|
|
|
+ Spi4RxFifoCtrlAddrLsb : begin
|
|
|
Spi4RxFifoCtrlReg[7:0] <= Data_i[7:0];
|
|
|
end
|
|
|
Spi4TxFifo : begin
|
|
|
@@ -887,10 +917,10 @@ always @(posedge Clk_i) begin
|
|
|
Spi5CsCtrlAddr : begin
|
|
|
Spi5CsCtrlReg[7:0] <= Data_i[7:0];
|
|
|
end
|
|
|
- Spi5TxFifoCtrlAddr : begin
|
|
|
+ Spi5TxFifoCtrlAddrLsb : begin
|
|
|
Spi5TxFifoCtrlReg[7:0] <= Data_i[7:0];
|
|
|
end
|
|
|
- Spi5RxFifoCtrlAddr : begin
|
|
|
+ Spi5RxFifoCtrlAddrLsb : begin
|
|
|
Spi5RxFifoCtrlReg[7:0] <= Data_i[7:0];
|
|
|
end
|
|
|
Spi5TxFifo : begin
|
|
|
@@ -911,10 +941,10 @@ always @(posedge Clk_i) begin
|
|
|
Spi6CsCtrlAddr : begin
|
|
|
Spi6CsCtrlReg[7:0] <= Data_i[7:0];
|
|
|
end
|
|
|
- Spi6TxFifoCtrlAddr : begin
|
|
|
+ Spi6TxFifoCtrlAddrLsb : begin
|
|
|
Spi6TxFifoCtrlReg[7:0] <= Data_i[7:0];
|
|
|
end
|
|
|
- Spi6RxFifoCtrlAddr : begin
|
|
|
+ Spi6RxFifoCtrlAddrLsb : begin
|
|
|
Spi6RxFifoCtrlReg[7:0] <= Data_i[7:0];
|
|
|
end
|
|
|
Spi6TxFifo : begin
|
|
|
@@ -962,12 +992,18 @@ always @(*) begin
|
|
|
Spi0CsCtrlAddr : begin
|
|
|
ansReg = Spi0CsCtrlReg;
|
|
|
end
|
|
|
- Spi0TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi0TxFifoCtrlReg;
|
|
|
+ Spi0TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg0_i[15:0];
|
|
|
end
|
|
|
- Spi0RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi0RxFifoCtrlReg;
|
|
|
+ Spi0TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg0_i[31:16];
|
|
|
+ end
|
|
|
+ Spi0RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg0_i[15:0];
|
|
|
end
|
|
|
+ Spi0RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg0_i[31:16];
|
|
|
+ end
|
|
|
Spi0TxFifo : begin
|
|
|
ansReg = Spi0TxFifoReg;
|
|
|
end
|
|
|
@@ -986,12 +1022,18 @@ always @(*) begin
|
|
|
Spi1CsCtrlAddr : begin
|
|
|
ansReg = Spi1CsCtrlReg;
|
|
|
end
|
|
|
- Spi1TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi1TxFifoCtrlReg;
|
|
|
+ Spi1TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg1_i[15:0];
|
|
|
end
|
|
|
- Spi1RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi1RxFifoCtrlReg;
|
|
|
+ Spi1TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg1_i[31:16];
|
|
|
+ end
|
|
|
+ Spi1RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg1_i[15:0];
|
|
|
end
|
|
|
+ Spi1RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg1_i[31:16];
|
|
|
+ end
|
|
|
Spi1TxFifo : begin
|
|
|
ansReg = Spi1TxFifoReg;
|
|
|
end
|
|
|
@@ -1010,12 +1052,18 @@ always @(*) begin
|
|
|
Spi2CsCtrlAddr : begin
|
|
|
ansReg = Spi2CsCtrlReg;
|
|
|
end
|
|
|
- Spi2TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi2TxFifoCtrlReg;
|
|
|
+ Spi2TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg2_i[15:0];
|
|
|
end
|
|
|
- Spi2RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi2RxFifoCtrlReg;
|
|
|
+ Spi2TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg2_i[31:16];
|
|
|
+ end
|
|
|
+ Spi2RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg2_i[15:0];
|
|
|
end
|
|
|
+ Spi2RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg2_i[31:16];
|
|
|
+ end
|
|
|
Spi2TxFifo : begin
|
|
|
ansReg = Spi2TxFifoReg;
|
|
|
end
|
|
|
@@ -1034,12 +1082,18 @@ always @(*) begin
|
|
|
Spi3CsCtrlAddr : begin
|
|
|
ansReg = Spi3CsCtrlReg;
|
|
|
end
|
|
|
- Spi3TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi3TxFifoCtrlReg;
|
|
|
+ Spi3TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg3_i[15:0];
|
|
|
end
|
|
|
- Spi3RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi3RxFifoCtrlReg;
|
|
|
+ Spi3TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg3_i[31:16];
|
|
|
+ end
|
|
|
+ Spi3RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg3_i[15:0];
|
|
|
end
|
|
|
+ Spi3RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg3_i[31:16];
|
|
|
+ end
|
|
|
Spi3TxFifo : begin
|
|
|
ansReg = Spi3TxFifoReg;
|
|
|
end
|
|
|
@@ -1058,12 +1112,18 @@ always @(*) begin
|
|
|
Spi4CsCtrlAddr : begin
|
|
|
ansReg = Spi4CsCtrlReg;
|
|
|
end
|
|
|
- Spi4TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi4TxFifoCtrlReg;
|
|
|
+ Spi4TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg4_i[15:0];
|
|
|
end
|
|
|
- Spi4RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi4RxFifoCtrlReg;
|
|
|
+ Spi4TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg4_i[31:16];
|
|
|
+ end
|
|
|
+ Spi4RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg4_i[15:0];
|
|
|
end
|
|
|
+ Spi4RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg4_i[31:16];
|
|
|
+ end
|
|
|
Spi4TxFifo : begin
|
|
|
ansReg = Spi4TxFifoReg;
|
|
|
end
|
|
|
@@ -1082,12 +1142,18 @@ always @(*) begin
|
|
|
Spi5CsCtrlAddr : begin
|
|
|
ansReg = Spi5CsCtrlReg;
|
|
|
end
|
|
|
- Spi5TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi5TxFifoCtrlReg;
|
|
|
+ Spi5TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg5_i[15:0];
|
|
|
end
|
|
|
- Spi5RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi5RxFifoCtrlReg;
|
|
|
+ Spi5TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg5_i[31:16];
|
|
|
+ end
|
|
|
+ Spi5RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg5_i[15:0];
|
|
|
end
|
|
|
+ Spi5RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg5_i[31:16];
|
|
|
+ end
|
|
|
Spi5TxFifo : begin
|
|
|
ansReg = Spi5TxFifoReg;
|
|
|
end
|
|
|
@@ -1106,12 +1172,18 @@ always @(*) begin
|
|
|
Spi6CsCtrlAddr : begin
|
|
|
ansReg = Spi6CsCtrlReg;
|
|
|
end
|
|
|
- Spi6TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi6TxFifoCtrlReg;
|
|
|
+ Spi6TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg6_i[15:0];
|
|
|
end
|
|
|
- Spi6RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi6RxFifoCtrlReg;
|
|
|
+ Spi6TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg6_i[31:16];
|
|
|
+ end
|
|
|
+ Spi6RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg6_i[15:0];
|
|
|
end
|
|
|
+ Spi6RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg6_i[31:16];
|
|
|
+ end
|
|
|
Spi6TxFifo : begin
|
|
|
ansReg = Spi6TxFifoReg;
|
|
|
end
|
|
|
@@ -1146,12 +1218,18 @@ always @(*) begin
|
|
|
Spi0CsCtrlAddr : begin
|
|
|
ansReg = Spi0CsCtrlReg[15:8];
|
|
|
end
|
|
|
- Spi0TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi0TxFifoCtrlReg[15:8];
|
|
|
+ Spi0TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg0_i[15:8];
|
|
|
end
|
|
|
- Spi0RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi0RxFifoCtrlReg[15:8];
|
|
|
+ Spi0TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg0_i[31:24];
|
|
|
+ end
|
|
|
+ Spi0RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg0_i[15:8];
|
|
|
end
|
|
|
+ Spi0RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg0_i[31:24];
|
|
|
+ end
|
|
|
Spi0TxFifo : begin
|
|
|
ansReg = Spi0TxFifoReg[15:8];
|
|
|
end
|
|
|
@@ -1170,12 +1248,18 @@ always @(*) begin
|
|
|
Spi1CsCtrlAddr : begin
|
|
|
ansReg = Spi1CsCtrlReg[15:8];
|
|
|
end
|
|
|
- Spi1TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi1TxFifoCtrlReg[15:8];
|
|
|
+ Spi1TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg1_i[15:8];
|
|
|
end
|
|
|
- Spi1RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi1RxFifoCtrlReg[15:8];
|
|
|
+ Spi1TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg1_i[31:24];
|
|
|
+ end
|
|
|
+ Spi1RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg1_i[15:8];
|
|
|
end
|
|
|
+ Spi1RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg1_i[31:24];
|
|
|
+ end
|
|
|
Spi1TxFifo : begin
|
|
|
ansReg = Spi1TxFifoReg[15:8];
|
|
|
end
|
|
|
@@ -1194,12 +1278,18 @@ always @(*) begin
|
|
|
Spi2CsCtrlAddr : begin
|
|
|
ansReg = Spi2CsCtrlReg[15:8];
|
|
|
end
|
|
|
- Spi2TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi2TxFifoCtrlReg[15:8];
|
|
|
+ Spi2TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg2_i[15:8];
|
|
|
end
|
|
|
- Spi2RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi2RxFifoCtrlReg[15:8];
|
|
|
+ Spi2TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg2_i[31:24];
|
|
|
+ end
|
|
|
+ Spi2RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg2_i[15:8];
|
|
|
end
|
|
|
+ Spi2RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg2_i[31:24];
|
|
|
+ end
|
|
|
Spi2TxFifo : begin
|
|
|
ansReg = Spi2TxFifoReg[15:8];
|
|
|
end
|
|
|
@@ -1218,12 +1308,18 @@ always @(*) begin
|
|
|
Spi3CsCtrlAddr : begin
|
|
|
ansReg = Spi3CsCtrlReg[15:8];
|
|
|
end
|
|
|
- Spi3TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi3TxFifoCtrlReg[15:8];
|
|
|
+ Spi3TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg3_i[15:8];
|
|
|
end
|
|
|
- Spi3RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi3RxFifoCtrlReg[15:8];
|
|
|
+ Spi3TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg3_i[31:24];
|
|
|
+ end
|
|
|
+ Spi3RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg3_i[15:8];
|
|
|
end
|
|
|
+ Spi3RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg3_i[31:24];
|
|
|
+ end
|
|
|
Spi3TxFifo : begin
|
|
|
ansReg = Spi3TxFifoReg[15:8];
|
|
|
end
|
|
|
@@ -1242,12 +1338,18 @@ always @(*) begin
|
|
|
Spi4CsCtrlAddr : begin
|
|
|
ansReg = Spi4CsCtrlReg[15:8];
|
|
|
end
|
|
|
- Spi4TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi4TxFifoCtrlReg[15:8];
|
|
|
+ Spi4TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg4_i[15:8];
|
|
|
end
|
|
|
- Spi4RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi4RxFifoCtrlReg[15:8];
|
|
|
+ Spi4TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg4_i[31:24];
|
|
|
+ end
|
|
|
+ Spi4RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg4_i[15:8];
|
|
|
end
|
|
|
+ Spi4RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg4_i[31:24];
|
|
|
+ end
|
|
|
Spi4TxFifo : begin
|
|
|
ansReg = Spi4TxFifoReg[15:8];
|
|
|
end
|
|
|
@@ -1266,12 +1368,18 @@ always @(*) begin
|
|
|
Spi5CsCtrlAddr : begin
|
|
|
ansReg = Spi5CsCtrlReg[15:8];
|
|
|
end
|
|
|
- Spi5TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi5TxFifoCtrlReg[15:8];
|
|
|
+ Spi5TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg5_i[15:8];
|
|
|
end
|
|
|
- Spi5RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi5RxFifoCtrlReg[15:8];
|
|
|
+ Spi5TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg5_i[31:24];
|
|
|
+ end
|
|
|
+ Spi5RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg5_i[15:8];
|
|
|
end
|
|
|
+ Spi5RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg5_i[31:24];
|
|
|
+ end
|
|
|
Spi5TxFifo : begin
|
|
|
ansReg = Spi5TxFifoReg[15:8];
|
|
|
end
|
|
|
@@ -1290,12 +1398,18 @@ always @(*) begin
|
|
|
Spi6CsCtrlAddr : begin
|
|
|
ansReg = Spi6CsCtrlReg[15:8];
|
|
|
end
|
|
|
- Spi6TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi6TxFifoCtrlReg[15:8];
|
|
|
+ Spi6TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg6_i[15:8];
|
|
|
end
|
|
|
- Spi6RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi6RxFifoCtrlReg[15:8];
|
|
|
+ Spi6TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg6_i[31:24];
|
|
|
+ end
|
|
|
+ Spi6RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg6_i[15:8];
|
|
|
end
|
|
|
+ Spi6RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg6_i[31:24];
|
|
|
+ end
|
|
|
Spi6TxFifo : begin
|
|
|
ansReg = Spi6TxFifoReg[15:8];
|
|
|
end
|
|
|
@@ -1330,12 +1444,18 @@ always @(*) begin
|
|
|
Spi0CsCtrlAddr : begin
|
|
|
ansReg = Spi0CsCtrlReg[7:0];
|
|
|
end
|
|
|
- Spi0TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi0TxFifoCtrlReg[7:0];
|
|
|
+ Spi0TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg0_i[7:0];
|
|
|
end
|
|
|
- Spi0RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi0RxFifoCtrlReg[7:0];
|
|
|
+ Spi0TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg0_i[23:16];
|
|
|
+ end
|
|
|
+ Spi0RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg0_i[7:0];
|
|
|
end
|
|
|
+ Spi0RxFifoCtrlAddrMsb : begin
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|
|
+ ansReg = RxFifoCtrlReg0_i[23:16];
|
|
|
+ end
|
|
|
Spi0TxFifo : begin
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|
|
ansReg = Spi0TxFifoReg[7:0];
|
|
|
end
|
|
|
@@ -1354,12 +1474,18 @@ always @(*) begin
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Spi1CsCtrlAddr : begin
|
|
|
ansReg = Spi1CsCtrlReg[7:0];
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|
|
end
|
|
|
- Spi1TxFifoCtrlAddr : begin
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|
|
- ansReg = Spi1TxFifoCtrlReg[7:0];
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|
+ Spi1TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg1_i[7:0];
|
|
|
end
|
|
|
- Spi1RxFifoCtrlAddr : begin
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|
- ansReg = Spi1RxFifoCtrlReg[7:0];
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|
+ Spi1TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg1_i[23:16];
|
|
|
+ end
|
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|
+ Spi1RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg1_i[7:0];
|
|
|
end
|
|
|
+ Spi1RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg1_i[23:16];
|
|
|
+ end
|
|
|
Spi1TxFifo : begin
|
|
|
ansReg = Spi1TxFifoReg[7:0];
|
|
|
end
|
|
|
@@ -1378,12 +1504,18 @@ always @(*) begin
|
|
|
Spi2CsCtrlAddr : begin
|
|
|
ansReg = Spi2CsCtrlReg[7:0];
|
|
|
end
|
|
|
- Spi2TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi2TxFifoCtrlReg[7:0];
|
|
|
+ Spi2TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg2_i[7:0];
|
|
|
end
|
|
|
- Spi2RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi2RxFifoCtrlReg[7:0];
|
|
|
+ Spi2TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg2_i[23:16];
|
|
|
+ end
|
|
|
+ Spi2RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg2_i[7:0];
|
|
|
end
|
|
|
+ Spi2RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg2_i[23:16];
|
|
|
+ end
|
|
|
Spi2TxFifo : begin
|
|
|
ansReg = Spi2TxFifoReg[7:0];
|
|
|
end
|
|
|
@@ -1402,12 +1534,18 @@ always @(*) begin
|
|
|
Spi3CsCtrlAddr : begin
|
|
|
ansReg = Spi3CsCtrlReg[7:0];
|
|
|
end
|
|
|
- Spi3TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi3TxFifoCtrlReg[7:0];
|
|
|
+ Spi3TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg3_i[7:0];
|
|
|
end
|
|
|
- Spi3RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi3RxFifoCtrlReg[7:0];
|
|
|
+ Spi3TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg3_i[23:16];
|
|
|
+ end
|
|
|
+ Spi3RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg3_i[7:0];
|
|
|
end
|
|
|
+ Spi3RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg3_i[23:16];
|
|
|
+ end
|
|
|
Spi3TxFifo : begin
|
|
|
ansReg = Spi3TxFifoReg[7:0];
|
|
|
end
|
|
|
@@ -1426,12 +1564,18 @@ always @(*) begin
|
|
|
Spi4CsCtrlAddr : begin
|
|
|
ansReg = Spi4CsCtrlReg[7:0];
|
|
|
end
|
|
|
- Spi4TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi4TxFifoCtrlReg[7:0];
|
|
|
+ Spi4TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg4_i[7:0];
|
|
|
end
|
|
|
- Spi4RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi4RxFifoCtrlReg[7:0];
|
|
|
+ Spi4TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg4_i[23:16];
|
|
|
+ end
|
|
|
+ Spi4RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg4_i[7:0];
|
|
|
end
|
|
|
+ Spi4RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg4_i[23:16];
|
|
|
+ end
|
|
|
Spi4TxFifo : begin
|
|
|
ansReg = Spi4TxFifoReg[7:0];
|
|
|
end
|
|
|
@@ -1450,12 +1594,18 @@ always @(*) begin
|
|
|
Spi5CsCtrlAddr : begin
|
|
|
ansReg = Spi5CsCtrlReg[7:0];
|
|
|
end
|
|
|
- Spi5TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi5TxFifoCtrlReg[7:0];
|
|
|
+ Spi5TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg5_i[7:0];
|
|
|
end
|
|
|
- Spi5RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi5RxFifoCtrlReg[7:0];
|
|
|
+ Spi5TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg5_i[23:16];
|
|
|
+ end
|
|
|
+ Spi5RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg5_i[7:0];
|
|
|
end
|
|
|
+ Spi5RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg5_i[23:16];
|
|
|
+ end
|
|
|
Spi5TxFifo : begin
|
|
|
ansReg = Spi5TxFifoReg[7:0];
|
|
|
end
|
|
|
@@ -1474,12 +1624,18 @@ always @(*) begin
|
|
|
Spi6CsCtrlAddr : begin
|
|
|
ansReg = Spi6CsCtrlReg[7:0];
|
|
|
end
|
|
|
- Spi6TxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi6TxFifoCtrlReg[7:0];
|
|
|
+ Spi6TxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg6_i[7:0];
|
|
|
end
|
|
|
- Spi6RxFifoCtrlAddr : begin
|
|
|
- ansReg = Spi6RxFifoCtrlReg[7:0];
|
|
|
+ Spi6TxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = TxFifoCtrlReg6_i[23:16];
|
|
|
+ end
|
|
|
+ Spi6RxFifoCtrlAddrLsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg6_i[7:0];
|
|
|
end
|
|
|
+ Spi6RxFifoCtrlAddrMsb : begin
|
|
|
+ ansReg = RxFifoCtrlReg6_i[23:16];
|
|
|
+ end
|
|
|
Spi6TxFifo : begin
|
|
|
ansReg = Spi6TxFifoReg[7:0];
|
|
|
end
|
Anatoliy Chigirinskiy