Merge branch 'Stepan_Changes'

SRAM/SRAM_tb.v

@@ -0,0 +1,208 @@
+`timescale 1ns / 1ps
+module SRAM_tb;
+
+reg Clk123;
+reg Clk50;
+wire Rst_i;
+reg writeEn_i;
+reg readEn_i;
+reg Start_i;
+
+
+reg [27:0] sramData;
+
+wire [15:0] sramDataOut;
+wire [11:0] sramAddrOut;
+wire fullFlag;
+wire emptyFlag;
+
+
+reg [4:0] cnt; 
+reg [2:0] trCnt;
+reg SS;
+reg outputEn_i;
+
+
+
+
+assign sramDataOut =sramData[15:0];
+// assign sramDataOut = (!outputEn_i)?16'bz:sramData[15:0];
+assign sramAddrOut = sramData[27:16];
+
+
+
+
+always #(4.065) Clk123 = ~Clk123;
+always #(10) Clk50 = ~Clk50;
+
+
+initial begin 
+    Clk123 = 1'b1;
+    Clk50 = 1'b1;
+    Start_i = 1'b0;
+    #1500 Start_i = 1'b1;
+    #500 Start_i = 1'b0;
+end
+
+
+
+
+
+always @(posedge Clk123) begin 
+    if (Rst_i) begin 
+        cnt <= 1'b0;
+    end
+    else begin  
+        if (cnt < 20 ) begin 
+            cnt <= cnt + 1'b1;
+        end
+        else begin 
+            cnt <= 1'b0;
+        end
+    end
+end
+
+
+always @(posedge Clk123) begin 
+    if (Rst_i) begin 
+        trCnt <= 1'b0;
+    end
+    else begin 
+        if (cnt == 20 ) begin 
+            trCnt <= trCnt + 1'b1;
+        end
+    end
+end
+
+
+always @(posedge Clk123) begin 
+    if (Rst_i) begin 
+        sramData <= 28'h00000000;
+    end
+    else begin 
+        case (trCnt) 
+            0 : begin 
+                sramData <= {11'h0, 16'h01};
+            end
+            1 : begin 
+                sramData <= {11'h02, 16'h00};
+            end
+        endcase
+    end
+end
+
+
+
+
+always @(negedge Clk123) begin 
+    if (Rst_i) begin 
+        SS <= 1'b1;
+    end
+    else begin 
+        if ( cnt >= 0 && cnt !== 9 ) begin 
+            SS <= 1'b0;
+        end
+        else begin 
+            SS <= 1'b1;
+        end
+    end
+end
+
+
+
+always @(negedge Clk123) begin 
+    if (Rst_i) begin 
+        writeEn_i <= 1'b1;
+    end
+    else begin 
+        if (cnt >= 2 && cnt <= 6 ) begin 
+            writeEn_i <= 1'b0;
+        end
+        else begin 
+            writeEn_i <= 1'b1;
+        end
+    end
+end
+
+
+always @(negedge Clk123) begin 
+    if (Rst_i) begin 
+        outputEn_i <= 1'b1;
+    end
+    else begin 
+        if (cnt >= 10 && cnt <= 19 ) begin 
+            outputEn_i <= 1'b0;
+        end
+        else begin 
+            outputEn_i <= 1'b1;
+        end
+    end
+end
+
+
+always @(negedge Clk123) begin 
+    if (Rst_i) begin 
+        readEn_i <= 1'b1;
+    end
+    else begin 
+        if ((cnt >= 13 && cnt <= 18) ) begin 
+            readEn_i <= 1'b0;
+        end
+        else begin 
+            readEn_i <= 1'b1;
+        end
+    end
+end
+
+
+
+
+// always @(posedge Clk_i) begin 
+//     if (Rst_i) begin 
+//         CE_i <= 1'b0;
+//     end
+//     else begin
+//         if (!fullFlag && ) begin
+//             CE_i <= 1'b1;
+//         end
+//         else begin
+//             CE_i <= 1'b0;
+//         end
+//     end
+// end
+
+
+SRAMr SRAMr_inst (
+    .Clk123_i(Clk123),
+    // .Clk50_i(Clk50),
+    // .Rst_i(Rst_i),
+    // .Start_i(Start_i),
+    .Addr_i(sramAddrOut),
+    .Data_i(),
+    .writeEn_i(writeEn_i),
+    .readEn_i(readEn_i)
+    // .fullFlag(fullFlag),
+    // .emptyFlag(emptyFlag),
+
+);
+
+
+
+
+InitRst InitRst_inst (
+    .clk_i(Clk123),
+    .signal_o(Rst_i)
+
+);
+
+
+
+
+
+
+
+
+
+endmodule
+
+

SRAM/SRAMr.v

@@ -0,0 +1,92 @@
+
+module SRAMr #(
+    parameter CmdRegWidth = 32,
+    parameter AddrRegWidth = 12
+
+) (
+    input Clk123_i,
+    // input Clk50_i,
+    input [AddrRegWidth-2:0] Addr_i,
+    inout [CmdRegWidth/2-1:0] Data_i,
+    // input Start_i,
+    input writeEn_i,
+    input readEn_i,
+    input [1:0] BE_i,
+    input outputEn_i,
+
+    // output wire fullFlag,
+    // output wire emptyFlag,
+    output  Led_o
+   
+
+
+
+
+
+
+
+
+);
+//testComment
+//================================================================================
+//  REG/WIRE
+//================================================================================
+
+    wire wrEn;
+    wire rdEn;
+    wire Rst_i;
+    wire [CmdRegWidth/2-1:0] data;
+    wire [AddrRegWidth-1:0] addr; 
+
+    wire mosi0;
+    wire mosi1;
+    wire mosi2;
+    wire mosi3;
+    wire sck;
+    wire ss;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign addr = {Addr_i, 1'b0};
+assign Data_i = (!outputEn_i) ? data : 16'bz;
+
+
+
+
+
+//================================================================================
+//  CODING
+//================================================================================	
+
+
+
+RegMap #(
+    .CmdRegWidth(32),
+    .AddrRegWidth(12)
+)
+RegMap_inst (
+    .Clk_i(Clk123_i),
+    .Rst_i(Rst_i),
+    .Data_i(Data_i),
+    .Addr_i(addr),
+    .wrEn_i(writeEn_i),
+    .rdEn_i(readEn_i),
+    .BE_i(BE_i),
+    .Led_o(Led_o),
+    .AnsDataReg_o(data)
+
+);
+
+
+InitRst InitRst_inst (
+    .clk_i(Clk123_i),
+    .signal_o(Rst_i)
+
+);
+
+
+
+
+
+endmodule

sources_1/new/DspSmc/DspSmcModel.v

@@ -0,0 +1,237 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01.09.2022 15:03:04
+// Design Name: 
+// Module Name: DspModel
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//
+//	2BYTES ADDRESING
+//	0->2->4->6
+//	
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	DspSmcModel
+#(
+	parameter	DwordsNum	=	5,
+	parameter	DataToClkRate	=	4,		//data changes every 4th clk negedge
+	parameter	SmcWrBaseAddr	=	4,		//data changes every 4th clk negedge
+	parameter	SmcRdBaseAddr	=	1,		//data changes every 4th clk negedge
+	parameter	[15:0]	SmcBaseData	=	16'h5,		//data changes every 4th clk negedge
+	parameter	Offset		=	2,		//data changes every 4th clk negedge
+	parameter	WordsNum	=	10		//data changes every 4th clk negedge
+)
+(
+	input	Clk120MHz_i,
+	input	RstN_i,
+	inout	[15:0]	SmcD_o,
+	output	[10:0]	SmcA_o,
+	output	SmcAwe_o,
+	output	SmcAmsN_o,
+	output	SmcAoe_o,
+	output	SmcAre_o,
+	output	[1:0]	SmcBe_o,
+	
+	input	Start_i
+);
+
+//================================================================================
+//  REG/WIRE
+	reg		smcAmsN;
+	reg		smcAoe;
+	reg		smcAwe;
+	reg		smcAre;
+	reg		[1:0]	smcBe;
+
+	reg	[1:0]	writeSetupDelay;
+	reg	[1:0]	writeAccessDelay;
+	reg	[1:0]	writeHoldDelay;
+	reg	[1:0]	transTurnDelay;
+	reg	[1:0]	readSetupDelay;
+	reg	[1:0]	readAccessDelay;
+	
+	reg	[24:0]	smcAddr;
+	reg	[15:0]	smcData;
+	
+	reg	[3:0]	currState;
+	
+	reg	[3:0]	wordsCnt;
+	
+	wire	txDone;
+//================================================================================
+//  LOCALPARAM
+
+	localparam	IDLE			=	3'h0;
+	localparam	WriteSetup		=	3'h1;
+	localparam	WriteAccess		=	3'h2;
+	localparam	WriteHold		=	3'h3;
+	localparam	TramsTurn		=	3'h4;
+	localparam	ReadSetup		=	3'h5;
+	localparam	ReadAccess		=	3'h6;
+	localparam	ReadHold		=	3'h7;
+	
+	
+//================================================================================
+//  ASSIGNMENTS	
+	assign	SmcA_o		=	smcAddr;
+	assign	SmcD_o		=	(!SmcAre_o)?	15'bz:smcData;
+	assign	SmcAwe_o	=	smcAwe;
+	assign	SmcAmsN_o	=	smcAmsN;
+	assign	SmcAoe_o	=	smcAoe;
+	assign	SmcAre_o	=	smcAre;
+	assign	SmcBe_o		=	smcBe;
+	
+	assign	txDone	=	wordsCnt==WordsNum-1;
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk120MHz_i	or	negedge	RstN_i)	begin
+	if	(!RstN_i)	begin
+		wordsCnt	<=	0;
+	end	else	begin
+		if	(currState	==	TramsTurn)	begin
+			if	(smcAmsN)	begin
+				if	(wordsCnt!=WordsNum-1)	begin
+					wordsCnt	<=	wordsCnt+4'd1;
+				end	else	begin
+					wordsCnt	<=	0;
+				end
+			end
+		end	
+	end
+end
+
+always	@(negedge	Clk120MHz_i	or	negedge	RstN_i)	begin
+	if	(!RstN_i)	begin
+		currState	<=	0;
+		smcAddr	<=	0;
+		smcData	<=	0;
+		smcAmsN	<=	1'b1;
+		smcAoe	<=	1'b1;
+		smcAwe	<=	1'b1;
+		smcAre	<=	1'b1;
+		smcBe	<=	2'b00;
+		writeSetupDelay	<=	2'b01;
+		writeAccessDelay<=	4'b01;
+		writeHoldDelay	<=	2'b01;
+		transTurnDelay	<=	2'b01;
+		readSetupDelay	<=	3'b01;
+		readAccessDelay	<=	5'b01;
+	end	else	begin
+		case(currState)
+		IDLE:		begin
+						if	(Start_i)	begin
+							currState	<=	WriteSetup;
+							smcAmsN	<=	1'b0;
+							smcAddr	<=	wordsCnt;
+							smcData	<=	wordsCnt;
+							smcAmsN	<=	1'b0;
+							smcAoe	<=	1'b1;
+							smcAre	<=	1'b1;
+							smcAwe	<=	1'b1;
+							smcBe	<=	2'b00;
+						end	else	begin
+							currState	<=	IDLE;
+						end
+					end
+					
+		WriteSetup:	begin
+						if	(writeSetupDelay[0])	begin
+							currState	<=	WriteAccess;
+							smcAwe	<=	1'b0;
+							writeSetupDelay	<=	2'b01;
+						end	else	begin
+							currState	<=	WriteSetup;
+							writeSetupDelay	<=	writeSetupDelay<<1;
+						end	
+					end
+					
+		WriteAccess:begin
+						if	(writeAccessDelay[0])	begin
+							currState	<=	WriteHold;
+							writeAccessDelay<=	4'b0001;
+							smcAwe	<=	1'b1;
+						end	else	begin
+							currState	<=	WriteAccess;	
+							writeAccessDelay<=	writeAccessDelay<<1;
+						end
+					end
+					
+		WriteHold	:begin
+						if	(writeHoldDelay[0])	begin
+							currState	<=	TramsTurn;
+							writeHoldDelay<=	2'b01;
+							smcAmsN	<=	1'b1;
+						end	else	begin
+							currState	<=	WriteHold;	
+							writeHoldDelay<=	writeHoldDelay<<1;
+						end
+					end
+					
+		TramsTurn	:begin
+							if	(transTurnDelay[0])	begin
+								if	(!txDone)	begin
+									currState	<=	WriteSetup;
+									smcAmsN	<=	1'b0;
+									smcAddr	<=	wordsCnt;
+									smcData	<=	wordsCnt;
+									smcAmsN	<=	1'b0;
+									smcAoe	<=	1'b1;
+									smcAre	<=	1'b1;
+									smcAwe	<=	1'b1;
+									smcBe	<=	2'b00;
+								end	else	begin
+									currState	<=	ReadSetup;
+									transTurnDelay<=	2'b01;
+									smcAmsN	<=	1'b0;
+									smcAoe	<=	1'b0;
+									smcAddr	<=	SmcRdBaseAddr;
+								end
+							end	else	begin
+									currState	<=	TramsTurn;	
+									transTurnDelay<=	transTurnDelay<<1;
+							end
+					end
+		ReadSetup	:begin
+						if	(readSetupDelay[0])	begin
+							currState	<=	ReadAccess;
+							readSetupDelay<=	3'b001;
+							smcAre	<=	1'b0;
+						end	else	begin
+							currState		<=	ReadSetup;	
+							readSetupDelay	<=	readSetupDelay<<1;
+						end
+					end
+		ReadAccess	:begin
+						if	(readAccessDelay[0])	begin
+							currState	<=	ReadHold;
+							readAccessDelay<=	5'b00001;
+							smcAre	<=	1'b1;
+						end	else	begin
+							currState		<=	ReadAccess;	
+							readAccessDelay	<=	readAccessDelay<<1;
+						end
+					end
+		ReadHold	:begin
+						currState	<=	IDLE;
+						smcAmsN	<=1'b1;
+						smcAoe	<=	1'b1;
+					end
+					
+		endcase
+	end
+end
+endmodule

sources_1/new/DspSmc/MasterFpgaTop.v

@@ -0,0 +1,78 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 10.10.2018 01:07:38
+// Design Name: 
+// Module Name: sram_ctrl2
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	MasterFpgaTop
+(
+	input	Clk_i,                       
+	input	RstN_i,                     
+	input	ForceRstN_i,                     
+
+	input	[15:0]	SmcD_i,
+	input	[24:0]	SmcA_i,
+	input	SmcAwe_i,
+	input	SmcAmsN_i,
+	input	SmcAoe_i,	
+	input	SmcAre_i,	
+	input	[1:0]	SmcBe_i,
+	
+	output	[15:0]	Data_o,
+	output	[24:0]	Addr_o,
+	output	Val_o
+);
+
+//================================================================================
+//  REG/WIRE
+	
+	wire	[24:0]	sramSmcAddr;
+	wire	[31:0]	sramSmcData;
+	wire	sramVal;
+
+//================================================================================
+//  LOCALPARAM
+	
+//================================================================================
+//  ASSIGNMENTS	
+
+//================================================================================
+//  CODING
+	
+
+SramRx	SramRx
+(
+	.Clk_i		(Clk_i	),
+	.RstN_i		(RstN_i),
+	.ForceRstN_i(ForceRstN_i),
+
+	.SmcD_i		(SmcD_i),
+	.SmcA_i		(SmcA_i),
+	.SmcAwe_i	(SmcAwe_i),
+	.SmcAmsN_i	(SmcAmsN_i),
+	.SmcAoe_i	(SmcAoe_i),
+	.SmcAre_i	(SmcAre_i),
+	.SmcBe_i	(SmcBe_i),
+	
+	.Data_o		(sramSmcData),
+	.Addr_o		(sramSmcAddr),
+	.Val_o		(sramVal)
+);
+
+endmodule

sources_1/new/DspSmc/MasterFpgaTopTb.v

@@ -0,0 +1,102 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 10.10.2018 01:07:38
+// Design Name: 
+// Module Name: sram_ctrl2
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	MasterFpgaTopTb
+(
+	input	Clk_i
+);
+
+//================================================================================
+//  REG/WIRE
+	reg	clk120Dsp;
+	reg	clk120Fpga;
+	reg	start;
+	reg	rstN;
+	reg	ForceRstN;
+	
+	wire	[15:0]	data;
+	wire	[24:0]	addr;
+	wire	awe;
+	wire	amsn;
+	wire	aoe;
+	wire	are;
+	wire	[1:0]	be;
+//================================================================================
+//  LOCALPARAM
+	
+//================================================================================
+//  ASSIGNMENTS	
+	always	#4.2	clk120Dsp	=	~clk120Dsp;
+	always	#4.2	clk120Fpga	=	~clk120Fpga;
+//================================================================================
+//  CODING
+
+initial	begin
+	rstN		=	0;
+	ForceRstN	=	0;
+	clk120Dsp	=	1;
+	start		=	0;
+	clk120Fpga	=	0;
+	#20
+	rstN		=	1;
+	ForceRstN	=	1;
+	#100
+	start	=	1;
+	#4.2
+	start	=	0;
+	
+end
+
+DspSramModel	DspSramInterface
+(
+	.Clk120MHz_i	(clk120Dsp),
+	.RstN_i			(rstN),
+	.SmcD_o			(data),
+	.SmcA_o			(addr),
+	.SmcAwe_o		(awe),
+	.SmcAmsN_o		(amsn),
+	.SmcAoe_o		(aoe),
+	.SmcAre_o		(are),
+	.SmcBe_o		(be),
+	
+	.Start_i		(start)
+);
+
+MasterFpgaTop	MasterFpgaTop
+(
+	.Clk_i		(clk120Fpga),
+	.RstN_i		(rstN),
+	.ForceRstN_i(ForceRstN),
+
+	.SmcD_i		(data),
+	.SmcA_i		(addr),
+	.SmcAwe_i	(awe),
+	.SmcAmsN_i	(amsn),
+	.SmcAoe_i	(aoe),
+	.SmcAre_i	(are),
+	.SmcBe_i	(be),
+	
+	.Data_o		(),
+	.Addr_o		(),
+	.Val_o		()
+);
+endmodule

sources_1/new/DspSmc/S5443_3TopTb.v

@@ -0,0 +1,113 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 10.10.2018 01:07:38
+// Design Name: 
+// Module Name: sram_ctrl2
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module	S5443_3TopTb
+(
+	input	Clk_i
+);
+
+//================================================================================
+//  REG/WIRE
+	reg	clk123Dsp;
+	wire	start;
+	reg	rstN;
+	reg	ForceRstN;
+	
+	wire	[15:0]	data;
+	wire	[10:0]	addr;
+	wire	awe;
+	wire	amsn;
+	wire	aoe;
+	wire	are;
+	wire	[1:0]	be;
+	
+	reg	[31:0]	tbCnt;
+//================================================================================
+//  LOCALPARAM
+	
+//================================================================================
+//  ASSIGNMENTS	
+	always	#8.13	clk123Dsp	=	~clk123Dsp;
+	assign	start	=	(tbCnt==50||tbCnt==51);
+//================================================================================
+//  CODING
+
+initial	begin
+	rstN		=	0;
+	ForceRstN	=	0;
+	clk123Dsp	=	1;
+	#20
+	rstN		=	1;
+	ForceRstN	=	1;
+	
+end
+
+always	@(posedge	clk123Dsp)	begin
+	if	(rstN)	begin
+		tbCnt	<=	tbCnt+32'd1;
+	end	else	begin
+		tbCnt	<=	0;
+	end
+end
+
+DspSmcModel	DspSmcModel
+(
+	.Clk120MHz_i	(clk123Dsp),
+	.RstN_i			(rstN),
+	.SmcD_o			(data),
+	.SmcA_o			(addr),
+	.SmcAwe_o		(awe),
+	.SmcAmsN_o		(amsn),
+	.SmcAoe_o		(aoe),
+	.SmcAre_o		(are),
+	.SmcBe_o		(be),
+	
+	.Start_i		(start)
+);
+
+S5443_3Top S5443_3Top
+(
+	.Clk123_i	(clk123Dsp),
+	.SmcAddr_i	(addr),
+	.SmcData_i	(data),
+    
+	.SmcAwe_i	(awe),
+	.SmcAmsN_i	(amsn),
+	
+	.SmcAre_i	(are),
+	.SmcBe_i	(be),
+	.SmcAoe_i	(aoe),
+	.LD_i		(),
+	
+	.Led_o		(),
+	
+	.Mosi0_o	(),
+	.Mosi1_o	(),
+	.Mosi2_o	(),
+	.Mosi3_o	(),
+	.Ss_o		(),
+	.SsFlash_o	(),
+	.Sck_o		(),
+	.SpiRst_o	(),
+	.LD_o		()
+);
+endmodule

sources_1/new/DspSmc/SmcRx.v

@@ -22,24 +22,24 @@
 
 module	SmcRx
 #(
-	parameter	DataOutWidth	=	16,
-	parameter	DataInWidth		=	16,
+	parameter	DataInOutWidth	=	16,
 	parameter	AddrWidth		=	12
 )
 (
 	input	Clk_i,                       
-	input	RstN_i,                     
-	input	ForceRstN_i,                     
+	input	Rst_i,                         
 
-	input	[DataInWidth-1:0]	SmcD_i,
-	input	[AddrWidth-1:0]	SmcA_i,
+	inout	[DataInOutWidth-1:0]	SmcD_i,
+	input	[AddrWidth-2:0]	SmcA_i,
 	input	SmcAwe_i,
 	input	SmcAmsN_i,
 	input	SmcAoe_i,
 	input	SmcAre_i,	
 	input	[1:0]	SmcBe_i,	
 	
-	output	[DataOutWidth-1:0]	Data_o,
+	input	[DataInOutWidth-1:0]	AnsData_i,
+	
+	output	[DataInOutWidth-1:0]	Data_o,
 	output	[AddrWidth-1:0]	Addr_o,
 	output	Val_o
 );
@@ -47,86 +47,46 @@ module	SmcRx
 //================================================================================
 //  REG/WIRE
 	
-	reg	[AddrWidth-1:0]	smcAddr;
-	reg	[DataInWidth-1:0]	smcData;
-	reg	val;
-	reg	valReg;
-	
-	reg	smcAwe;
-	reg	smcAweR;
-	reg	smcAweRR;
-	
-	reg	smcAmsN;
-	reg	smcAmsNR;
-	
-	wire	smcAweNeg	=	(!smcAweRR&smcAweR);
 	
+	reg	[DataInOutWidth-1:0]	inDataReg;
+	reg	[AddrWidth-1:0]			addrReg;
+	reg	valReg;
 	
-	reg	[DataOutWidth-1:0]	dataOutReg;
-	reg	[AddrWidth-1:0]		addrDataReg;
-
+	reg	[DataInOutWidth-1:0]	outDataReg;
 //================================================================================
 //  LOCALPARAM
 
 //================================================================================
 //  ASSIGNMENTS	
-	assign	Data_o	=	dataOutReg;
-	assign	Addr_o	=	addrDataReg;
+	assign	Data_o	=	inDataReg;
+	assign	Addr_o	=	addrReg;
 	assign	Val_o	=	valReg;
 	
-	
+	assign	SmcD_i	=	(!SmcAre_i)?	outDataReg:15'bz;
 //================================================================================
 //  CODING
 	
-always	@(posedge	Clk_i)	begin
-	if	(RstN_i&ForceRstN_i)	begin
-		smcAmsN		<=	SmcAmsN_i;
-		smcAmsNR	<=	smcAmsN;
-		
-		smcAwe		<=	SmcAwe_i;
-		smcAweR		<=	smcAwe;
-		smcAweRR	<=	smcAweR;
-	end	else	begin
-		smcAmsN		<=	0;
-		smcAmsNR	<=	0;
-		
-		smcAwe		<=	0;
-		smcAweR		<=	0;
-		smcAweRR	<=	0;
-	end
-end
-	
-always	@(posedge	Clk_i)	begin
-	if	(RstN_i&ForceRstN_i)	begin
-		if	(!smcAmsNR)	begin
-			if	(smcAweNeg)	begin
-				smcData	<=	SmcD_i;
-				smcAddr	<=	SmcA_i;
-				val		<=	1;
+always	@(posedge	Clk_i	or	negedge	Rst_i)	begin
+	if	(!Rst_i)	begin
+		if	(!SmcAmsN_i)	begin
+			if	(!SmcAwe_i)	begin
+				addrReg	<=	{SmcA_i,1'b0};
+				inDataReg	<=	SmcD_i;
+				valReg	<=	1'b1;
 			end	else	begin
-				val		<=	0;
+				valReg	<=	0;
 			end
+			
+			if	(!SmcAoe_i)	begin
+				addrReg		<=	{SmcA_i,1'b0};
+				outDataReg	<=	AnsData_i;
+			end	
 		end
 	end	else	begin
-		smcData	<=	0;
-		smcAddr	<=	0;
-		val		<=	0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(RstN_i&ForceRstN_i)	begin
-		if	(val)	begin
-			addrDataReg	<=	smcAddr;
-			dataOutReg	<=	{dataOutReg[DataInWidth-1:0],smcData};
-			valReg	<=	val;
-		end	else	begin
-			valReg	<=	1'b0;
-		end
-	end	else	begin
-		dataOutReg	<=	0;
-		addrDataReg	<=	0;
-		valReg	<=	1'b0;
+		inDataReg	<=	0;
+		outDataReg	<=	0;
+		addrReg	<=	0;
+		valReg		<=	0;
 	end
 end
 

sources_1/new/MMCM/MmcmWrapper.v

@@ -16,19 +16,12 @@ module MmcmWrapper
 wire            clkfb_bufgout;
 wire            clkfb_bufgin;
 wire            clk0_bufgin;
-wire            clk0_bufgout;
 wire            clk1_bufgin;
-wire            clk1_bufgout;
 wire            clk2_bufgin;
-wire            clk2_bufgout;
 wire            clk3_bufgin;
-wire            clk3_bufgout;
 wire            clk4_bufgin;
-wire            clk4_bufgout;
 wire            clk5_bufgin;
-wire            clk5_bufgout;
 wire            clk6_bufgin;
-wire            clk6_bufgout;
 
 //================================================================================
 //	ASSIGNMENTS

sources_1/new/Mux/DataMuxer.v

@@ -1,18 +1,34 @@
 
 module SmcDataMux 
 #(
-    parameter	CmdRegWidth	=	32,
+    parameter	CmdRegWidth	=	16,
     parameter	AddrRegWidth=	12,
 	
 	parameter	FifoNum	=	7,
 	
-	parameter	Fifo0WriteAddr	=	12'h0+12'h24,
-	parameter	Fifo1WriteAddr	=	12'h50+12'h24,
-	parameter	Fifo2WriteAddr	=	12'hF0+12'h24,
-	parameter	Fifo3WriteAddr	=	12'h140+12'h24,
-	parameter	Fifo4WriteAddr	=	12'h190+12'h24,
-	parameter	Fifo5WriteAddr	=	12'h1e0+12'h24,
-	parameter	Fifo6WriteAddr	=	12'h230+12'h24
+	// parameter	Fifo0WriteLsbAddr	=	12'h0+12'h24,
+	// parameter	Fifo0WriteMsbAddr	=	12'h0+12'h26,
+	// parameter	Fifo1WriteLsbAddr	=	12'h50+12'h24,
+	// parameter	Fifo2WriteMsbAddr	=	12'hF0+12'h26,
+	// parameter	Fifo3WriteLsbAddr	=	12'h140+12'h24,
+	// parameter	Fifo4WriteMsbAddr	=	12'h190+12'h26,
+	// parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h24,
+	// parameter	Fifo6WriteMsbAddr	=	12'h230+12'h26
+	
+	parameter	Fifo0WriteLsbAddr	=	12'h0+12'h0,
+	parameter	Fifo0WriteMsbAddr	=	12'h0+12'h2,
+	parameter	Fifo1WriteLsbAddr	=	12'h0+12'h4,
+	parameter	Fifo1WriteMsbAddr	=	12'h0+12'h6,
+	parameter	Fifo2WriteLsbAddr	=	12'h0+12'h8,
+	parameter	Fifo2WriteMsbAddr	=	12'h00+12'ha,
+	parameter	Fifo3WriteLsbAddr	=	12'h0+12'hc,
+	parameter	Fifo3WriteMsbAddr	=	12'h0+12'he,
+	parameter	Fifo4WriteLsbAddr	=	12'h0+12'h10,
+	parameter	Fifo4WriteMsbAddr	=	12'h190+12'h9,
+	parameter	Fifo5WriteLsbAddr	=	12'h1e0+12'h10,
+	parameter	Fifo5WriteMsbAddr	=	12'h1e0+12'h11,
+	parameter	Fifo6WriteLsbAddr	=	12'h230+12'h12,
+	parameter	Fifo6WriteMsbAddr	=	12'h230+12'h13
 )
 (
     input	Clk_i,
@@ -27,13 +43,21 @@ module SmcDataMux
     output	reg	[AddrRegWidth-1:0]	ToRegMapAddr_o,
 	
 	output	reg	[FifoNum-1:0]	ToFifoVal_o,
-	output	reg	[CmdRegWidth*FifoNum-1:0]	ToFifoData_o
+	output	reg	[CmdRegWidth*2*FifoNum-1:0]	ToFifoData_o
 	
 );
 //================================================================================
 //	REG/WIRE
 //================================================================================
-
+	wire	requestToFifo0	=	(SmcAddr_i==Fifo0WriteLsbAddr||SmcAddr_i==Fifo0WriteMsbAddr);
+	wire	requestToFifo1	=	(SmcAddr_i==Fifo1WriteLsbAddr||SmcAddr_i==Fifo1WriteMsbAddr);
+	wire	requestToFifo2	=	(SmcAddr_i==Fifo2WriteLsbAddr||SmcAddr_i==Fifo2WriteMsbAddr);
+	wire	requestToFifo3	=	(SmcAddr_i==Fifo3WriteLsbAddr||SmcAddr_i==Fifo3WriteMsbAddr);
+	wire	requestToFifo4	=	(SmcAddr_i==Fifo4WriteLsbAddr||SmcAddr_i==Fifo4WriteMsbAddr);
+	wire	requestToFifo5	=	(SmcAddr_i==Fifo5WriteLsbAddr||SmcAddr_i==Fifo5WriteMsbAddr);
+	wire	requestToFifo6	=	(SmcAddr_i==Fifo6WriteLsbAddr||SmcAddr_i==Fifo6WriteMsbAddr);
+	
+	wire	requestToFifo	=	(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6);
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
@@ -49,41 +73,69 @@ module SmcDataMux
 always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 	if	(Rst_i)	begin
 		ToRegMapVal_o	<=	1'b0;
-		ToRegMapData_o	<=	32'h0;
+		ToRegMapData_o	<=	16'h0;
 		ToRegMapAddr_o	<=	12'h0;
 		
 		ToFifoVal_o		<=	7'h0;
-		ToFifoData_o	<=	32'h0;
+		ToFifoData_o	<=	16'h0;
 	end	else	begin
-		if	(SmcAddr_i	==	Fifo0WriteAddr||SmcAddr_i==Fifo1WriteAddr||SmcAddr_i==Fifo2WriteAddr||SmcAddr_i==Fifo3WriteAddr||SmcAddr_i==Fifo4WriteAddr||SmcAddr_i==Fifo5WriteAddr||SmcAddr_i==Fifo6WriteAddr)	begin	
+		if	(requestToFifo)	begin	
 			case(SmcAddr_i)	
-				Fifo0WriteAddr:	begin
+				Fifo0WriteLsbAddr:	begin
+									ToFifoVal_o[0]	<=	1'b0;
+									ToFifoData_o[CmdRegWidth*0+:CmdRegWidth]	<=	SmcData_i;
+								end
+				Fifo0WriteMsbAddr:	begin
 									ToFifoVal_o[0]	<=	SmcVal_i;
-									ToFifoData_o[32*0+:32]	<=	SmcData_i;
+									ToFifoData_o[CmdRegWidth*1+:CmdRegWidth]	<=	SmcData_i;
+								end
+				Fifo1WriteLsbAddr:	begin
+									ToFifoVal_o[1]	<=	1'b0;
+									ToFifoData_o[CmdRegWidth*2+:CmdRegWidth]	<=	SmcData_i;
 								end
-				Fifo1WriteAddr:	begin
+				Fifo1WriteMsbAddr:	begin
 									ToFifoVal_o[1]	<=	SmcVal_i;
-									ToFifoData_o[32*1-1+:32]	<=	SmcData_i;
+									ToFifoData_o[CmdRegWidth*3+:CmdRegWidth]	<=	SmcData_i;
 								end
-				Fifo2WriteAddr:	begin
+				Fifo2WriteLsbAddr:	begin
+									ToFifoVal_o[2]	<=	1'b0;
+									ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
+								end
+				Fifo2WriteMsbAddr:	begin
 									ToFifoVal_o[2]	<=	SmcVal_i;
-									ToFifoData_o[32*2-1+:32]	<=	SmcData_i;
+									ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
+								end
+				Fifo3WriteLsbAddr:	begin
+									ToFifoVal_o[3]	<=	1'b0;
+									ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
 								end
-				Fifo3WriteAddr:	begin
+				Fifo3WriteMsbAddr:	begin
 									ToFifoVal_o[3]	<=	SmcVal_i;
-									ToFifoData_o[32*3-1+:32]	<=	SmcData_i;
+									ToFifoData_o[CmdRegWidth*7+:CmdRegWidth]	<=	SmcData_i;
+								end
+				Fifo4WriteLsbAddr:	begin
+									ToFifoVal_o[4]	<=	1'b0;
+									ToFifoData_o[CmdRegWidth*8+:CmdRegWidth]	<=	SmcData_i;
 								end
-				Fifo4WriteAddr:	begin
+				Fifo4WriteMsbAddr:	begin
 									ToFifoVal_o[4]	<=	SmcVal_i;
-									ToFifoData_o[32*4-1+:32]	<=	SmcData_i;
+									ToFifoData_o[CmdRegWidth*9+:CmdRegWidth]	<=	SmcData_i;
 								end
-				Fifo5WriteAddr:	begin
+				Fifo5WriteLsbAddr:	begin
+									ToFifoVal_o[5]	<=	1'b0;
+									ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
+								end
+				Fifo5WriteMsbAddr:	begin
 									ToFifoVal_o[5]	<=	SmcVal_i;
-									ToFifoData_o[32*5-1+:32]	<=	SmcData_i;
+									ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
+								end
+				Fifo6WriteLsbAddr:	begin
+									ToFifoVal_o[6]	<=	1'b0;
+									ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
 								end
-				Fifo6WriteAddr:	begin
+				Fifo6WriteMsbAddr:	begin
 									ToFifoVal_o[6]	<=	SmcVal_i;
-									ToFifoData_o[32*6-1+:32]	<=	SmcData_i;
+									ToFifoData_o[CmdRegWidth*13+:CmdRegWidth]	<=	SmcData_i;
 								end
 			endcase
 		end	else	begin

sources_1/new/S5443_3Top.v

@@ -21,12 +21,14 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 
-module S5443_3Top #(
+module S5443_3Top 
+#(
     parameter CmdRegWidth = 32,
     parameter AddrRegWidth = 12,
     parameter SpiNum = 7
 
-)(
+)
+(
     input Clk123_i,
     input [AddrRegWidth-2:0] SmcAddr_i,
     inout [CmdRegWidth/2-1:0] SmcData_i,
@@ -141,7 +143,7 @@ wire [CmdRegWidth-1:0] GPIOA;
 
 
 wire	[AddrRegWidth-1:0]	toRegMapAddr;
-wire	[CmdRegWidth-1:0]	toRegMapData;
+wire	[CmdRegWidth/2-1:0]	toRegMapData;
 wire	toRegMapVal;
 
 wire	[SpiNum-1:0]	toFifoVal;
@@ -173,14 +175,13 @@ wire	[SpiNum-1:0]	spiClkBus;
 wire	[SpiNum-1:0]	spiSyncRst;
 
 wire	[AddrRegWidth-1:0]	smcAddr;
-wire	[CmdRegWidth-1:0]	smcData;
+wire	[CmdRegWidth/2-1:0]	smcData;
 wire	smcVal;
 	
+wire	[CmdRegWidth/2-1:0]	ansData;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-assign addr = {SmcAddr_i, 1'b0};
-assign Data_i = (!SmcAoe_i) ? data : 16'bz;
 assign ten = SpiTxRxEn[6:0];
 assign Mosi0_o = Mosi0;
 assign Mosi1_o = Mosi1;
@@ -361,17 +362,18 @@ BUFG BUFG_inst (
 SmcRx	SmcRx
 (
 	.Clk_i		(gclk),
-	.RstN_i		(!initRst),
-	.ForceRstN_i(1'b0),
+	.Rst_i		(initRst),
 
 	.SmcD_i		(SmcData_i),
-	.SmcA_i		(addr),
+	.SmcA_i		(SmcAddr_i),
 	.SmcAwe_i	(SmcAwe_i),
 	.SmcAmsN_i	(SmcAmsN_i),
 	.SmcAoe_i	(SmcAoe_i),
 	.SmcAre_i	(SmcAre_i),
 	.SmcBe_i	(SmcBe_i),
 	
+	.AnsData_i	(ansData),
+	
 	.Data_o		(smcData),
 	.Addr_o		(smcAddr),
 	.Val_o		(smcVal)
@@ -382,9 +384,9 @@ SmcDataMux SmcDataMuxer
     .Clk_i	(gclk),
     .Rst_i	(initRst),
 
-	.SmcVal_i	(1'b1),
-	.SmcData_i	({SmcData_i,SmcData_i}),
-    .SmcAddr_i	({SmcAddr_i,1'b0}),
+	.SmcVal_i	(smcVal),
+	.SmcData_i	(smcData),
+    .SmcAddr_i	(smcAddr),
 
 	.ToRegMapVal_o	(toRegMapVal),
 	.ToRegMapData_o	(toRegMapData),
@@ -395,20 +397,21 @@ SmcDataMux SmcDataMuxer
 	
 );
 
-RegMap #(
+RegMap 
+#(
     .CmdRegWidth(32),
     .AddrRegWidth(12)
 )
-RegMap_inst (
+RegMap_inst 
+(
     .Clk_i(gclk),
     .Rst_i(initRst),
     .Data_i(toRegMapData),
     .Addr_i(toRegMapAddr),
-    .wrEn_i(SmcAwe_i|toRegMapVal),
-    .rdEn_i(SmcAre_i),
+    .Val_i(toRegMapVal),
     .SmcBe_i(SmcBe_i),
     .Led_o(Led_o),
-    .AnsDataReg_o(data),
+    .AnsDataReg_o(ansData),
     //Spi0
     .Spi0CtrlReg_o(Spi0Ctrl),
     .Spi0ClkReg_o(Spi0Clk),
@@ -475,7 +478,6 @@ RegMap_inst (
 
     .SpiTxRxEnReg_o(SpiTxRxEn),
     .GPIOAReg_o(GPIOA)
-
 );
 
 MmcmWrapper MainMmcm
@@ -492,20 +494,20 @@ genvar i;
 generate
     for  (i = 0; i < SpiNum; i = i + 1) begin: SpiGen
 		
-		RstSync SpiRstSync
-		(
-			.Clk_i	(spiClkBus[i]),
-			.Rst_i	(initRst),
+		// RstSync SpiRstSync
+		// (
+			// .Clk_i	(spiClkBus[i]),
+			// .Rst_i	(initRst),
 
-			.Rst_o	(spiSyncRst[i])
-		);
+			// .Rst_o	(spiSyncRst[i])
+		// );
 		
 		DataFifoWrapper DataFifoWrapper
 		(
 			.WrClk_i	(gclk),
 			.RdClk_i	(spiClkBus[i]),
-			// .Rst_i		(initRst | FifoRxRst[i]),
-			.Rst_i		(spiSyncRst[i] | FifoRxRst[i]),
+			// .Rst_i		(spiSyncRst[i] | FifoRxRst[i]),
+			.Rst_i		(FifoRxRst[i]),
             .SmcAre_i   (SmcAre_i),
 	
 			.ToFifoVal_i	(toFifoVal[i]),
@@ -541,10 +543,10 @@ generate
 endgenerate
 
 
-InitRst InitRst_inst (
+InitRst InitRst_inst
+ (
     .clk_i(gclk),
     .signal_o(initRst)
-
 );