Рефакторинг топ модуля

sources_1/new/S5443_3Top.v

@@ -61,29 +61,20 @@ module S5443_3Top
 //  REG/WIRE
 //================================================================================
 	wire clk80;
-	wire [SpiNum-1:0]sckMuxed;
 	wire [AddrRegWidth-1:0] addrExt;
-	wire [SpiNum-1:0] ssMuxed; 
-	wire [SpiNum-1:0]mosi0;
-	wire [SpiNum-1:0]mosi1;
-	wire [SpiNum-1:0]mosi2;
-	wire [SpiNum-1:0]mosi3;
+
+	wire [SpiNum-1:0] mosi3;
 	wire [SpiNum-1:0] txEn;
-	wire [SpiNum-1:0] spiTxEnSync;
+
 	wire initRst;
 	wire gclk;
+
 	wire [0:7] baudRate [SpiNum-1:0];
 	
 	wire [0:31] txFifoCtrlReg [SpiNum-1:0];
 	wire [0:31] rxFifoCtrlReg [SpiNum-1:0];
 	
-	
-	
-	
-	
 	//InitRst
-	
-	wire [SpiNum-1:0] initRstGen;
 	wire rst80;
 
 	//SPI0
@@ -204,23 +195,19 @@ module S5443_3Top
 	wire [CmdRegWidth-1:0] spi6CsCtrlRR;
 	wire [CmdRegWidth-1:0] spi6TxFifoCtrlRR;
 	wire [CmdRegWidth-1:0] spi6RxFifoCtrlRR;
-
-	
 	
 	wire [CmdRegWidth-1:0] spiTxRxEn;
-	wire [CmdRegWidth-1:0] GPIOA;
-	wire [CmdRegWidth-1:0] GPIOASync;
-	
+	wire [CmdRegWidth-1:0] Gpio;
 	
-	wire	[AddrRegWidth-1:0]	toRegMapAddr;
-	wire	[CmdRegWidth/2-1:0]	toRegMapData;
-	wire	toRegMapVal;
+	wire [AddrRegWidth-1:0]	toRegMapAddr;
+	wire [CmdRegWidth/2-1:0]	toRegMapData;
+	wire toRegMapVal;
 	
-	wire	[SpiNum-1:0]	toFifoVal;
-	wire	[CmdRegWidth*SpiNum-1:0]	toFifoData;
+	wire [SpiNum-1:0]	toFifoVal;
+	wire [CmdRegWidth*SpiNum-1:0]	toFifoData;
 	
-	wire	[SpiNum-1:0]	toSpiVal;
-	wire	[0:31]	toSpiData [SpiNum-1:0];
+	wire [SpiNum-1:0]	toSpiVal;
+	wire [0:31]	toSpiData [SpiNum-1:0];
 	
 	wire [0:1] widthSel [SpiNum-1:0];
 	wire [SpiNum-1:0] clockPol;
@@ -229,7 +216,6 @@ module S5443_3Top
 	wire [SpiNum-1:0] selSt;
 	wire [SpiNum-1:0] spiMode;
 	
-	
 	wire [0:5] stopDelay [SpiNum-1:0];
 	wire [SpiNum-1:0] leadx;
 	wire [SpiNum-1:0] lag; 
@@ -240,58 +226,28 @@ module S5443_3Top
 	wire [0:7]  wordCntTx [SpiNum-1:0];
 	wire [0:7]  wordCntRx [SpiNum-1:0];
 	
-	
 	wire [SpiNum-1:0] chipSelFpga;
 	wire [SpiNum-1:0] chipSelFlash;
 	
 	wire [SpiNum-1:0] assel;
 	
 	wire	[SpiNum-1:0]	spiClkBus;
-	wire	[SpiNum-1:0]	spiSyncRst;
-	wire	[AddrRegWidth-1:0]	smcAddr;
-	wire	[CmdRegWidth/2-1:0]	smcData;
-	wire	smcVal;
+
 	//RxFifo 
-	wire [0:31] dataToRxFifo [SpiNum-1:0];
-	wire [0:7] addrToRxFifo [SpiNum-1:0];
-	wire [SpiNum-1:0] valToRxFifo;
-	wire [SpiNum-1:0] valToTxFifoRead;
-	
-	
-	// SPI mode choice 
-	wire [SpiNum-1:0] sckR; 
-	wire [SpiNum-1:0] ssR;
-	wire [SpiNum-1:0] mosi0R;
-	wire [SpiNum-1:0] valReg;
-	wire [SpiNum-1:0] valToTxR;
-	wire [SpiNum-1:0] valToRxR;
-	wire [0:31] dataToRxFifoR [SpiNum-1:0];
-	
-	
-	wire [SpiNum-1:0] sckQ;
-	wire [SpiNum-1:0] ssQ;
-	wire [SpiNum-1:0] mosi0Q;
-	wire [SpiNum-1:0] valToTxQ;
-	wire [SpiNum-1:0] valToRxQ;
-	wire [0:31] dataToRxFifoQ [SpiNum-1:0];
 	wire [0:31] dataFromRxFifo [SpiNum-1:0];
 	
 	wire [CmdRegWidth/2-1:0] muxedData;
 	
 	wire smcValComb; 
-	wire	[CmdRegWidth/2-1:0]	ansData;
+	wire [CmdRegWidth/2-1:0]	ansData;
 
 	wire requestToFifo;
 
-	wire [SpiNum-1: 0] emptyFlagTx;
-
 	wire [SpiNum-1:0] spiEn;
 
 	wire [SpiNum-1:0] ldReg;
 
-
-	reg [SpiNum-1:0] ssReg;
-	reg [SpiNum-1:0] ssFlashReg;
+	wire [SpiNum-1:0] ssW;
 
 	//================================================================================
 	//  ASSIGNMENTS
@@ -299,14 +255,7 @@ module S5443_3Top
 	assign addrExt = {SmcAddr_i, 1'b0};
 	assign smcValComb = (!SmcAmsN_i && !SmcAwe_i) ? 1'b1 : 1'b0;
 	assign txEn = spiTxRxEn[6:0];
-	assign Mosi1_io[0] =(SpiDir_o[0])?mosi1[0]:1'bz;
-	assign Mosi1_io[1] =(SpiDir_o[1])?mosi1[1]:1'bz;
-	assign Mosi1_io[2] =(SpiDir_o[2])?mosi1[2]:1'bz;
-	assign Mosi1_io[3] =(SpiDir_o[3])?mosi1[3]:1'bz;
-	assign Mosi1_io[4] =(SpiDir_o[4])?mosi1[4]:1'bz;
-	assign Mosi1_io[5] =(SpiDir_o[5])?mosi1[5]:1'bz;
-	assign Mosi1_io[6] =(SpiDir_o[6])?mosi1[6]:1'bz;
-	assign Mosi2_o = mosi2;
+
 	assign Mosi3_o[0] = mosi3[0];
 	assign Mosi3_o[1] = mosi3[1];
 	assign Mosi3_o[2] = mosi3[2];
@@ -315,26 +264,9 @@ module S5443_3Top
 	// assign Mosi3_o[5] = mosi3[5];
 	assign Mosi3_o[5] = mosi3[6];// Mosi6 
 
-
-	assign Ss_o[0]       = (assel[0]) ? (chipSelFpga[0] ? ssMuxed[0] : 1'b1) : chipSelFpga[0];
-	assign Ss_o[1]       = (assel[1]) ? (chipSelFpga[1] ? ssMuxed[1] : 1'b1) : chipSelFpga[1];
-	assign Ss_o[2]       = (assel[2]) ? (chipSelFpga[2] ? ssMuxed[2] : 1'b1) : chipSelFpga[2];
-	assign Ss_o[3]       = (assel[3]) ? (chipSelFpga[3] ? ssMuxed[3] : 1'b1) : chipSelFpga[3];
-	assign Ss_o[4]       = (assel[4]) ? (chipSelFpga[4] ? ssMuxed[4] : 1'b1) : chipSelFpga[4];
-	assign Ss_o[5]       = (assel[5]) ? (chipSelFpga[5] ? ssMuxed[5] : 1'b1) : chipSelFpga[5];
-	assign Ss_o[6]       = (assel[6]) ? (chipSelFpga[6] ? ssMuxed[6] : 1'b1) : chipSelFpga[6];
-	assign LoCsReg_o     = (assel[5]) ? (chipSelFpga[5] ? ssMuxed[5] : 1'b1) : chipSelFpga[5];
-
-	assign SsFlash_o[0] = (assel[0]) ? (chipSelFlash[0] ? ssMuxed[0] : 1'b1) : chipSelFlash[0];
-	assign SsFlash_o[1] = (assel[1]) ? (chipSelFlash[1] ? ssMuxed[1] : 1'b1) : chipSelFlash[1];
-	assign SsFlash_o[2] = (assel[2]) ? (chipSelFlash[2] ? ssMuxed[2] : 1'b1) : chipSelFlash[2];
-	assign SsFlash_o[3] = (assel[3]) ? (chipSelFlash[3] ? ssMuxed[3] : 1'b1) : chipSelFlash[3];
-	assign SsFlash_o[4] = (assel[4]) ? (chipSelFlash[4] ? ssMuxed[4] : 1'b1) : chipSelFlash[4];
-	assign SsFlash_o[5] = (assel[5]) ? (chipSelFlash[5] ? ssMuxed[5] : 1'b1) : chipSelFlash[5];
-	assign SsFlash_o[6] = (assel[6]) ? (chipSelFlash[6] ? ssMuxed[6] : 1'b1) : chipSelFlash[6];
-
-	assign Sck_o = sckMuxed;
-
+	assign Ss_o			= ssW;
+	assign LoCsReg_o	= ssW[5];
+	
 	assign widthSel[0] = spi0CtrlRR[6:5];
 	assign widthSel[1] = spi1CtrlRR[6:5];
 	assign widthSel[2] = spi2CtrlRR[6:5];
@@ -431,13 +363,13 @@ module S5443_3Top
 	assign baudRate[5] = spi5Clk[7:0];
 	assign baudRate[6] = spi6Clk[7:0];
 	
-	assign SpiRst_o[0] = GPIOA[0];
-	assign SpiRst_o[1] = GPIOA[1];
-	assign SpiRst_o[2] = GPIOA[2];
-	assign SpiRst_o[3] = GPIOA[3];
-	assign SpiRst_o[4] = GPIOA[4];
-	assign SpiRst_o[5] = GPIOA[5];
-	assign SpiRst_o[6] = GPIOA[6];
+	assign SpiRst_o[0] = Gpio[0];
+	assign SpiRst_o[1] = Gpio[1];
+	assign SpiRst_o[2] = Gpio[2];
+	assign SpiRst_o[3] = Gpio[3];
+	assign SpiRst_o[4] = Gpio[4];
+	assign SpiRst_o[5] = Gpio[5];
+	assign SpiRst_o[6] = Gpio[6];
 	
 	assign fifoRxRstRdPtr[0] = spi0RxFifoCtrl[0];
 	assign fifoRxRstRdPtr[1] = spi1RxFifoCtrl[0];
@@ -505,14 +437,6 @@ module S5443_3Top
 	assign chipSelFlash[5] = spi5CsCtrlRR[1];
 	assign chipSelFlash[6] = spi6CsCtrlRR[1];
 	
-	assign ssMuxed[0] = (spiMode[0])? ssQ[0]:ssR[0];
-	assign ssMuxed[1] = (spiMode[1])? ssQ[1]:ssR[1];
-	assign ssMuxed[2] = (spiMode[2])? ssQ[2]:ssR[2];
-	assign ssMuxed[3] = (spiMode[3])? ssQ[3]:ssR[3];
-	assign ssMuxed[4] = (spiMode[4])? ssQ[4]:ssR[4];
-	assign ssMuxed[5] = (spiMode[5])? ssQ[5]:ssR[5];
-	assign ssMuxed[6] = (spiMode[6])? ssQ[6]:ssR[6];
-	
 	assign SpiDir_o[0] = (spiMode[0])? 1'b1 : 1'b0 ;
 	assign SpiDir_o[1] = (spiMode[1])? 1'b1 : 1'b0 ;
 	assign SpiDir_o[2] = (spiMode[2])? 1'b1 : 1'b0 ;
@@ -521,48 +445,6 @@ module S5443_3Top
 	assign SpiDir_o[5] = 1'b1;
 	assign SpiDir_o[6] = (spiMode[6])? 1'b1 : 1'b0 ;
 	
-	assign sckMuxed[0] =  (spiMode[0])?sckQ[0]:sckR[0];
-	assign sckMuxed[1] =  (spiMode[1])?sckQ[1]:sckR[1];
-	assign sckMuxed[2] =  (spiMode[2])?sckQ[2]:sckR[2];
-	assign sckMuxed[3] =  (spiMode[3])?sckQ[3]:sckR[3];
-	assign sckMuxed[4] =  (spiMode[4])?sckQ[4]:sckR[4];
-	assign sckMuxed[5] =  (spiMode[5])?sckQ[5]:sckR[5];
-	assign sckMuxed[6] =  (spiMode[6])?sckQ[6]:sckR[6];
-	
-	assign mosi0[0] =  (spiMode[0])?mosi0Q[0]:mosi0R[0];
-	assign mosi0[1] =  (spiMode[1])?mosi0Q[1]:mosi0R[1];
-	assign mosi0[2] =  (spiMode[2])?mosi0Q[2]:mosi0R[2];
-	assign mosi0[3] =  (spiMode[3])?mosi0Q[3]:mosi0R[3];
-	assign mosi0[4] =  (spiMode[4])?mosi0Q[4]:mosi0R[4];
-	assign mosi0[5] =  (spiMode[5])?mosi0Q[5]:mosi0R[5];
-	assign mosi0[6] =  (spiMode[6])?mosi0Q[6]:mosi0R[6];
-	
-	assign Mosi0_o = mosi0;
-	
-	assign valToTxFifoRead[0] =  (spiMode[0])?valToTxQ[0]:valToTxR[0];
-	assign valToTxFifoRead[1] =  (spiMode[1])?valToTxQ[1]:valToTxR[1];
-	assign valToTxFifoRead[2] =  (spiMode[2])?valToTxQ[2]:valToTxR[2];
-	assign valToTxFifoRead[3] =  (spiMode[3])?valToTxQ[3]:valToTxR[3];
-	assign valToTxFifoRead[4] =  (spiMode[4])?valToTxQ[4]:valToTxR[4];
-	assign valToTxFifoRead[5] =  (spiMode[5])?valToTxQ[5]:valToTxR[5];
-	assign valToTxFifoRead[6] =  (spiMode[6])?valToTxQ[6]:valToTxR[6];
-	
-	assign valToRxFifo[0] = valToRxR[0];
-	assign valToRxFifo[1] = valToRxR[1];
-	assign valToRxFifo[2] = valToRxR[2];
-	assign valToRxFifo[3] = valToRxR[3];
-	assign valToRxFifo[4] = valToRxR[4];
-	assign valToRxFifo[5] = valToRxR[5];
-	assign valToRxFifo[6] = valToRxR[6];
-	
-	assign dataToRxFifo[0] = dataToRxFifoR[0];
-	assign dataToRxFifo[1] = dataToRxFifoR[1];
-	assign dataToRxFifo[2] = dataToRxFifoR[2];
-	assign dataToRxFifo[3] = dataToRxFifoR[3];
-	assign dataToRxFifo[4] = dataToRxFifoR[4];
-	assign dataToRxFifo[5] = dataToRxFifoR[5];
-	assign dataToRxFifo[6] = dataToRxFifoR[6];
-	
 	assign spi0TxFifoCtrlReg = txFifoCtrlReg[0];
 	assign spi1TxFifoCtrlReg = txFifoCtrlReg[1];
 	assign spi2TxFifoCtrlReg = txFifoCtrlReg[2];
@@ -579,7 +461,7 @@ module S5443_3Top
 	assign spi5RxFifoCtrlReg = rxFifoCtrlReg[5];
 	assign spi6RxFifoCtrlReg = rxFifoCtrlReg[6];
 	
-	assign	SmcData_io	=	(!SmcAre_i && !SmcAoe_i)?muxedData:16'bz;
+	assign	SmcData_io	=	(!SmcAre_i && !SmcAoe_i) ? muxedData : 16'bz;
 	
 	//================================================================================
 	//  CODING
@@ -685,8 +567,8 @@ module S5443_3Top
 		.Spi0Ctrl_o			(spi0CtrlRR),
 		.Spi0CsCtrl_o		(spi0CsCtrlRR),
 		.Spi0CsDelay_o		(spi0CsDelayRR),
-		.Spi0TxFifoCtrl_o(spi0TxFifoCtrlRR),
-		.Spi0RxFifoCtrl_o(spi0RxFifoCtrlRR),
+		.Spi0TxFifoCtrl_o	(spi0TxFifoCtrlRR),
+		.Spi0RxFifoCtrl_o	(spi0RxFifoCtrlRR),
 
 		.Spi1Ctrl_o			(spi1CtrlRR),
 		.Spi1CsCtrl_o		(spi1CsCtrlRR),
@@ -808,7 +690,7 @@ module S5443_3Top
 		.Spi6RxFifoCtrlReg_o	(spi6RxFifoCtrl),
 		
 		.SpiTxRxEnReg_o			(spiTxRxEn),
-		.GPIOAReg_o				(GPIOA),
+		.GPIOAReg_o				(Gpio),
 
 		.AnsDataReg_o			(ansData),
 		.Led_o					(Led_o)
@@ -834,129 +716,68 @@ module S5443_3Top
 	);
 	 
 	genvar i;
-	
-	generate
-		for  (i = 0; i < SpiNum; i = i + 1) begin: SpiGen
-
-			InitRst InitRst_inst 
-			(
-				.clk_i(spiClkBus[i]),
-				.signal_o(initRstGen[i])
-			);
-
-			xpm_cdc_single #(
-				.DEST_SYNC_FF(3),
-				.INIT_SYNC_FF(0),
-				.SIM_ASSERT_CHK(0),
-				.SRC_INPUT_REG(1)
-			)
-			xpm_cdc_single_inst(
-				.dest_out(ldReg[i]),
+	generate 
+		for (i = 0; i < SpiNum; i = i+1) begin : SpiSubSystem
+
+			SpiSubSystem #(
+				.STAGES(STAGES),
+				.CmdRegWidth(CmdRegWidth),
+				.AddrRegWidth(AddrRegWidth),
+				.WIDTH(1)
+			) SpiSubSystem(
+				.Clk123_i(gclk),
+				.SpiClk_i(spiClkBus[i]),
 
-				.dest_clk(gclk),
-				.src_clk(spiClkBus[i]),
-				.src_in(Ld_i[i])
-			);
-
-			Sync1bit#(
-				.WIDTH(1),
-				.STAGES(STAGES)
-
-			)
-			Sync1bit_inst(
-				.ClkFast_i(gclk),
-				.ClkSlow_i(spiClkBus[i]),
 				.TxEn_i(txEn[i]),
-				.RstReg_i(GPIOA[i]),
-				.TxEn_o(spiTxEnSync[i]),
-				.RstReg_o(GPIOASync[i])
 
-			);
-			
-			DataFifoWrapper #(
-				.STAGES(STAGES)
-				
-			)DataFifoWrapper
-			(
-				.WrClk_i(gclk),
-				.RdClk_i(spiClkBus[i]),
-		
 				.FifoRxRst_i(fifoRxRst[i]),
 				.FifoTxRst_i(fifoTxRst[i]),
 				.FifoRxRstRdPtr_i(fifoRxRstRdPtr[i]),
 				.FifoTxRstWrPtr_i(fifoTxRstWrPtr[i]),
-
 				.SmcAre_i(SmcAre_i),
 				.SmcAwe_i(SmcAwe_i),
 				.SmcAddr_i(addrExt),
 				.ToFifoVal_i(toFifoVal[i]),
-				.ToFifoRxData_i(dataToRxFifo[i]),
-				.ToFifoRxWriteVal_i(valToRxFifo[i]),
-				.ToFifoTxReadVal_i(valToTxFifoRead[i]),
 				.ToFifoData_i(toFifoData[32*i+:32]),
-
-				.TxFifoCtrlReg_o(txFifoCtrlReg[i]),
-				.RxFifoCtrlReg_o(rxFifoCtrlReg[i]),
-				.EmptyFlagTx_o(emptyFlagTx[i]),
-				.DataFromRxFifo_o(dataFromRxFifo[i]),
-				.ToSpiData_o(toSpiData[i])
-			);
-	
-			SPIm SPIm_inst (
-				.Clk_i(spiClkBus[i]),
-				.Start_i(spiTxEnSync[i]),
-				.Rst_i(initRstGen[i]| spiMode[i] | !spiEn[i]),
-				.EmptyFlag_i(emptyFlagTx[i]),
-				.SpiData_i(toSpiData[i]),
-				.Sck_o(sckR[i]),
-				.Ss_o(ssR[i]),
-				.Mosi0_o(mosi0R[i]),
 				.WidthSel_i(widthSel[i]),
 				.PulsePol_i(clockPol[i]),
 				.ClockPhase_i(clockPhase[i]),
 				.EndianSel_i(endianSel[i]),
+				.ChipSelFlash_i(chipSelFlash[i]),
+				.ChipSelFpga_i(chipSelFpga[i]),
+				.Assel_i(assel[i]),
 				.Lag_i(lag[i]),
 				.Lead_i(leadx[i]),
-				.Stop_i(stopDelay[i]),
-				.SelSt_i(selSt[i]),
-				.Val_o(valToTxR[i])
-	
-			);
-	
-			SPIs SPIs_inst (
-				.Clk_i(spiClkBus[i]),
-				.Rst_i(initRstGen[i] | spiMode[i]),
-				.Sck_i(sckR[i]),
-				.Ss_i(ssR[i]),
-				.Mosi0_i(Mosi1_io[i]),
-				.WidthSel_i(widthSel[i]),
-				.EndianSel_i(endianSel[i]),
 				.SelSt_i(selSt[i]),
-				.DataToRxFifo_o(dataToRxFifoR[i]),
-				.Val_o(valToRxR[i])
-			);
-	
-			QuadSPIm QuadSPIm_inst (
-				.Clk_i(spiClkBus[i]),
-				.Start_i(spiTxEnSync[i]),
-				.Rst_i(initRstGen[i]| !spiMode[i] | !spiEn[i]),
-				.EmptyFlag_i(emptyFlagTx[i]),
-				.SpiData_i(toSpiData[i]),
-				.Sck_o(sckQ[i]),
-				.Ss_o(ssQ[i]),
-				.Mosi0_o(mosi0Q[i]),
-				.Mosi1_o(mosi1[i]),
-				.Mosi2_o(mosi2[i]),
-				.Mosi3_o(mosi3[i]),
-				.WidthSel_i(widthSel[i]),
-				.PulsePol_i(clockPol[i]),
-				.ClockPhase_i(clockPhase[i]),
-				.EndianSel_i(endianSel[i]),
-				.Lag_i(lag[i]),
-				.Lead_i(leadx[i]),
 				.Stop_i(stopDelay[i]),
-				.SelSt_i(selSt[i]),
-				.Val_o(valToTxQ[i])
+				.SpiMode_i(spiMode[i]),
+				.SpiEn_i(spiEn[i]),
+				
+				.TxFifoCtrlReg_o(txFifoCtrlReg[i]),
+				.RxFifoCtrlReg_o(rxFifoCtrlReg[i]),
+				.DataFromRxFifo_o(dataFromRxFifo[i]),
+
+				.Sck_o(Sck_o[i]),
+				.Ss_o(ssW[i]),
+				.SsFlash_o(SsFlash_o[i]),
+				.Mosi0_o(Mosi0_o[i]),
+				.Mosi1_io(Mosi1_io[i]),
+				.Mosi2_o(Mosi2_o[i]),
+				.Mosi3_o(mosi3[i])
+			);
+			
+			xpm_cdc_single #(
+				.DEST_SYNC_FF(3),
+				.INIT_SYNC_FF(0),
+				.SIM_ASSERT_CHK(0),
+				.SRC_INPUT_REG(1)
+			)
+			xpm_cdc_single_inst(
+				.dest_out(ldReg[i]),
+
+				.dest_clk(gclk),
+				.src_clk(spiClkBus[i]),
+				.src_in(Ld_i[i])
 			);
 		end
 	endgenerate

sources_1/new/SpiSubSystem/SpiLinesMuxer.v

@@ -0,0 +1,38 @@
+module SpiLinesMuxer (
+    input SsR_i,
+    input SsQ_i,
+    input SckR_i,
+    input SckQ_i,
+    input Mosi0R_i,
+    input Mosi0Q_i,
+
+    input ChipSelFpga_i,
+    input ChipSelFlash_i,
+    input Assel_i,
+    input SpiMode_i,
+
+    output Ss_o,
+    output SsFlash_o,
+    output Sck_o,
+    output Mosi0_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+wire ssMuxed;
+wire sckMuxed;
+wire mosi0Muxed;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign sckMuxed = (SpiMode_i) ? SckQ_i : SckR_i;
+assign ssMuxed = (SpiMode_i) ? SsQ_i : SsR_i;
+assign mosi0Muxed = (SpiMode_i) ? Mosi0Q_i : Mosi0R_i;
+
+assign Ss_o = (Assel_i) ? (ChipSelFpga_i ? ssMuxed : 1'b1) : ChipSelFpga_i;
+assign SsFlash_o = (Assel_i) ? (ChipSelFlash_i ? ssMuxed:1'b1) : ChipSelFlash_i;
+assign Sck_o = sckMuxed;
+assign Mosi0_o = mosi0Muxed;
+
+endmodule

sources_1/new/SpiSubSystem/SpiSubSystem.v

@@ -0,0 +1,199 @@
+module SpiSubSystem #(
+    parameter STAGES = 3,
+    parameter CmdRegWidth = 32,
+    parameter AddrRegWidth = 12,
+    parameter WIDTH  = 1 
+) (
+    input Clk123_i,
+    input SpiClk_i,
+
+    input TxEn_i,
+
+    input FifoRxRst_i,
+    input FifoTxRst_i,
+    input FifoRxRstRdPtr_i,
+    input FifoTxRstWrPtr_i,
+    input SmcAre_i,
+    input SmcAwe_i,
+    input [AddrRegWidth-1:0] SmcAddr_i,
+    input ToFifoVal_i,
+    input [CmdRegWidth-1:0] ToFifoData_i,
+
+    input [1:0] WidthSel_i,
+    input PulsePol_i,
+    input ClockPhase_i,
+    input EndianSel_i,
+    input Lag_i,
+    input Lead_i,
+    input SelSt_i,
+    input [5:0] Stop_i,
+    input Assel_i,
+
+    input ChipSelFpga_i,
+    input ChipSelFlash_i,
+
+    input SpiMode_i,
+    input SpiEn_i,
+
+    output [CmdRegWidth-1:0] TxFifoCtrlReg_o,
+    output [CmdRegWidth-1:0] RxFifoCtrlReg_o,
+    output [CmdRegWidth-1:0] DataFromRxFifo_o,
+
+    output Sck_o,
+    output Ss_o,
+    output SsFlash_o,
+    output Mosi0_o,
+    inout Mosi1_io,
+    output Mosi2_o,
+    output Mosi3_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+wire [CmdRegWidth-1:0] toSpiData;
+wire emptyFlagTx;
+wire initRst;
+
+wire sckR;
+wire ssR;
+wire mosi0R;
+wire valToTxR;
+wire valToRxR;
+
+wire sckQ;
+wire ssQ;
+wire mosi0Q;
+wire valToTxQ;
+
+wire valToTxFifoRead;
+wire valToRxFifoWrite;
+wire [CmdRegWidth-1:0] dataToRxFifo;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign valToTxFifoRead  = (SpiMode_i) ? valToTxQ : valToTxR;
+
+assign Mosi1_io = (SpiMode_i) ? mosi1_o : 1'bz;
+//================================================================================
+//	CODING
+//================================================================================
+InitRst InitRst_inst
+(
+    .clk_i(SpiClk_i),
+    .signal_o(initRst)
+
+);
+
+Sync1bit #(
+    .WIDTH(1),
+    .STAGES(STAGES)
+) Sync1bit_inst (
+    .ClkFast_i(Clk123_i),
+    .ClkSlow_i(SpiClk_i),
+    .TxEn_i(TxEn_i),
+    .TxEn_o(spiTxEnSync)
+);
+
+DataFifoWrapper #(
+    .STAGES(STAGES)
+) DataFifoWrapper
+(
+    .WrClk_i(Clk123_i),
+    .RdClk_i(SpiClk_i),
+
+    .FifoRxRst_i(FifoRxRst_i),
+    .FifoTxRst_i(FifoTxRst_i),
+    .FifoRxRstRdPtr_i(FifoRxRstRdPtr_i),
+    .FifoTxRstWrPtr_i(FifoTxRstWrPtr_i),
+
+    .SmcAre_i(SmcAre_i),
+    .SmcAwe_i(SmcAwe_i),
+    .SmcAddr_i(SmcAddr_i),
+    .ToFifoVal_i(ToFifoVal_i),
+    .ToFifoRxData_i(dataToRxFifo),
+    .ToFifoRxWriteVal_i(valToRxR),
+    .ToFifoTxReadVal_i(valToTxFifoRead),
+    .ToFifoData_i(ToFifoData_i),
+
+    .TxFifoCtrlReg_o(TxFifoCtrlReg_o),
+    .RxFifoCtrlReg_o(RxFifoCtrlReg_o),
+    .EmptyFlagTx_o(emptyFlagTx),
+    .DataFromRxFifo_o(DataFromRxFifo_o),
+    .ToSpiData_o(toSpiData)
+);
+
+SPIm SPIm_inst (
+    .Clk_i(SpiClk_i),
+    .Start_i(spiTxEnSync),
+    .Rst_i(initRst | SpiMode_i | !SpiEn_i),
+    .EmptyFlag_i(emptyFlagTx),
+    .SpiData_i(toSpiData),
+    .WidthSel_i(WidthSel_i),
+    .PulsePol_i(PulsePol_i),
+    .ClockPhase_i(ClockPhase_i),
+    .EndianSel_i(EndianSel_i),
+    .Lag_i(Lag_i),
+    .Lead_i(Lead_i),
+    .Stop_i(Stop_i),
+    .SelSt_i(SelSt_i),
+    .Sck_o(sckR),
+    .Ss_o(ssR),
+    .Mosi0_o(mosi0R),
+    .Val_o(valToTxR)
+);
+
+SPIs SPIs_inst (
+    .Clk_i(SpiClk_i),
+    .Rst_i(initRst | SpiMode_i),
+    .Sck_i(sckR),
+    .Ss_i(ssR),
+    .Mosi0_i(Mosi1_io),
+    .WidthSel_i(WidthSel_i),
+    .EndianSel_i(EndianSel_i),
+    .SelSt_i(SelSt_i),
+    .DataToRxFifo_o(dataToRxFifo),
+    .Val_o(valToRxR)
+);
+
+QuadSPIm QuadSPIm_inst (
+    .Clk_i(SpiClk_i),
+    .Start_i(spiTxEnSync),
+    .Rst_i(initRst | !SpiMode_i | !SpiEn_i),
+    .EmptyFlag_i(emptyFlagTx),
+    .SpiData_i(toSpiData),
+    .WidthSel_i(WidthSel_i),
+    .PulsePol_i(PulsePol_i),
+    .ClockPhase_i(ClockPhase_i),
+    .EndianSel_i(EndianSel_i),
+    .Lag_i(Lag_i),
+    .Lead_i(Lead_i),
+    .Stop_i(Stop_i),
+    .SelSt_i(SelSt_i),
+    .Sck_o(sckQ),
+    .Ss_o(ssQ),
+    .Mosi0_o(mosi0Q),
+    .Mosi1_o(mosi1_o),
+    .Mosi2_o(Mosi2_o),
+    .Mosi3_o(Mosi3_o),
+    .Val_o(valToTxQ)
+);
+
+SpiLinesMuxer SpiLinesMuxer (
+    .SsR_i(ssR),
+    .SsQ_i(ssQ),
+    .SckR_i(sckR),
+    .SckQ_i(sckQ),
+    .Mosi0R_i(mosi0R),
+    .Mosi0Q_i(mosi0Q),
+    .ChipSelFpga_i(ChipSelFpga_i),
+    .ChipSelFlash_i(ChipSelFlash_i),
+    .Assel_i(Assel_i),
+    .SpiMode_i(SpiMode_i),
+    .Ss_o(Ss_o),
+    .SsFlash_o(SsFlash_o),
+    .Sck_o(Sck_o),
+    .Mosi0_o(Mosi0_o)
+);
+
+endmodule