Рефакторинг модулей группы DataFifoWrapper

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -1,43 +1,58 @@
-
+//////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		
+// 
+// Create Date:		10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:		SpiSubSystem
+// Project Name:	S5443_V3_FPGA3
+// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description: 	
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 module DataFifoWrapper 
 #(
-    parameter	CmdRegWidth	=	32,
-    parameter	AddrRegWidth=	12,
-	parameter	STAGES		=	3,
-	
-	parameter	FifoNum	=	7
+	parameter	CMD_REG_WIDTH	=	32,
+	parameter	ADDR_REG_WIDTH	=	12,
+	parameter	STAGES			=	3,
+	parameter	FIFO_NUM		=	7
 )
 (
-    input	WrClk_i,
+	input	WrClk_i,
 	input	RdClk_i,
-    input	FifoRxRst_i,
+	input	FifoRxRst_i,
 	input	FifoTxRst_i,
 	input	FifoTxRstWrPtr_i,
 	input	FifoRxRstRdPtr_i,
-	input   SmcAre_i,
+	input	SmcAre_i,
 	input	SmcAwe_i,
-	input	[AddrRegWidth-1:0]	SmcAddr_i,
-	// input   [7:0] TxFifoWrdCnt_i,
-	// input   [7:0] RxFifoWrdCnt_i,
+	input	[ADDR_REG_WIDTH-1:0]	SmcAddr_i,
 
 	input	ToFifoVal_i,
-	input	[CmdRegWidth-1:0]	ToFifoData_i,
-	input   [CmdRegWidth-1:0]	ToFifoRxData_i,
-	input   ToFifoRxWriteVal_i,                   
+	input	[CMD_REG_WIDTH-1:0]	ToFifoData_i,
+	input	[CMD_REG_WIDTH-1:0]	ToFifoRxData_i,
+	input	ToFifoRxWriteVal_i,
 	
-	input ToFifoTxReadVal_i,
+	input	ToFifoTxReadVal_i,
 
 	output	ToSpiVal_o,
-	output EmptyFlagTx_o,
-	output [CmdRegWidth-1:0]	TxFifoCtrlReg_o,
-	output [CmdRegWidth-1:0]	RxFifoCtrlReg_o,
-	output	[CmdRegWidth-1:0]	ToSpiData_o,
-	output  [CmdRegWidth-1:0]   DataFromRxFifo_o
+	output	EmptyFlagTx_o,
+	output	[CMD_REG_WIDTH-1:0]	TxFifoCtrlReg_o,
+	output	[CMD_REG_WIDTH-1:0]	RxFifoCtrlReg_o,
+	output	[CMD_REG_WIDTH-1:0]	ToSpiData_o,
+	output	[CMD_REG_WIDTH-1:0]	DataFromRxFifo_o
 );
 //================================================================================
 //	REG/WIRE
 //================================================================================
-	wire [CmdRegWidth-1:0]	dataFromRxFifo;
+	wire [CMD_REG_WIDTH-1:0]	dataFromRxFifo;
 	wire fullFlagRx;
 	wire emptyFlagRx;
 	wire fullFlagTx;
@@ -52,19 +67,17 @@ module DataFifoWrapper
 	wire [7:0] txFifoUpDnCnt;
 
 	(* dont_touch = "true" *) wire emptyFlagTxForDsp;
-
-	//  (* dont_touch = "true" *)wire [6:0] wrDataCnt;
-	//  (* dont_touch = "true" *)wire [6:0] rdDataCnt;
 	
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
-	assign	ToSpiVal_o	=	1'b1;
+	assign ToSpiVal_o = 1'b1;
 	assign DataFromRxFifo_o = dataFromRxFifo;
 	assign EmptyFlagTx_o = emptyFlagTx;
 
-	assign TxFifoCtrlReg_o = {16'h0, txFifoUpDnCnt,5'h0,emptyFlagTxForDsp,fullFlagTx, FifoTxRst_i};
-	assign RxFifoCtrlReg_o = {16'h0, rxFifoUpDnCnt,5'h0,emptyFlagRx,fullFlagRx, FifoRxRst_i};
+	assign TxFifoCtrlReg_o = {16'h0, txFifoUpDnCnt, 5'h0, emptyFlagTxForDsp, fullFlagTx, FifoTxRst_i};
+	assign RxFifoCtrlReg_o = {16'h0, rxFifoUpDnCnt, 5'h0, emptyFlagRx, fullFlagRx, FifoRxRst_i};
+
 //================================================================================
 //	LOCALPARAMS
 //================================================================================
@@ -72,41 +85,34 @@ module DataFifoWrapper
 //================================================================================
 //	CODING
 //================================================================================
-
-	FifoCtrl FifoCtrl_inst (
-		.ToFifoTxWriteVal_i	(ToFifoVal_i),
-		.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
-		.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
-		.ToFifoRxReadVal_i	(!SmcAre_i),
-		.SmcAddr_i			(SmcAddr_i),
-		.FifoTxFull_i		(fullFlagTx),
-		.FifoTxRst_i		(FifoTxRst_i),
-		.FifoRxRst_i		(FifoRxRst_i),
-		.FifoTxRstWrPtr_i	(FifoTxRstWrPtr_i),
-		.FifoRxRstRdPtr_i	(FifoRxRstRdPtr_i),
-		.FifoTxEmpty_i		(emptyFlagTx),
-		.FifoRxFull_i		(fullFlagRx),
-		.EmptyFlagTxForDsp_o(emptyFlagTxForDsp),
-		.FifoRxEmpty_i		(emptyFlagRx),
-		.FifoTxWrClock_i	(WrClk_i),
-		.FifoTxRdClock_i	(RdClk_i),
-		.FifoRxWrClock_i	(RdClk_i),
-		.FifoRxRdClock_i	(WrClk_i),
-		.RxFifoUpDnCnt_o	(rxFifoUpDnCnt),
-		.TxFifoUpDnCnt_o	(txFifoUpDnCnt),
-		.FifoTxWriteEn_o	(txFifoWrEn),
-		.FifoTxReadEn_o		(txFifoRdEn),
-		.FifoRxWriteEn_o	(rxFifoWrEn),
-		.FifoRxReadEn_o		(rxFifoRdEn)
-	
-	
-	
-	
-	
+	FifoCtrl FifoCtrl_inst 
+	(
+		.ToFifoTxWriteVal_i		(ToFifoVal_i),
+		.ToFifoTxReadVal_i		(ToFifoTxReadVal_i),
+		.ToFifoRxWriteVal_i		(ToFifoRxWriteVal_i),
+		.ToFifoRxReadVal_i		(!SmcAre_i),
+		.SmcAddr_i				(SmcAddr_i),
+		.FifoTxFull_i			(fullFlagTx),
+		.FifoTxRst_i			(FifoTxRst_i),
+		.FifoRxRst_i			(FifoRxRst_i),
+		.FifoTxRstWrPtr_i		(FifoTxRstWrPtr_i),
+		.FifoRxRstRdPtr_i		(FifoRxRstRdPtr_i),
+		.FifoTxEmpty_i			(emptyFlagTx),
+		.FifoRxFull_i			(fullFlagRx),
+		.EmptyFlagTxForDsp_o	(emptyFlagTxForDsp),
+		.FifoRxEmpty_i			(emptyFlagRx),
+		.FifoTxWrClock_i		(WrClk_i),
+		.FifoTxRdClock_i		(RdClk_i),
+		.FifoRxWrClock_i		(RdClk_i),
+		.FifoRxRdClock_i		(WrClk_i),
+		.RxFifoUpDnCnt_o		(rxFifoUpDnCnt),
+		.TxFifoUpDnCnt_o		(txFifoUpDnCnt),
+		.FifoTxWriteEn_o		(txFifoWrEn),
+		.FifoTxReadEn_o			(txFifoRdEn),
+		.FifoRxWriteEn_o		(rxFifoWrEn),
+		.FifoRxReadEn_o			(rxFifoRdEn)
 	);
 	
-	
-	
 	DataFifoTx	DataFifoTx
 	( 
 		.wr_clk		(WrClk_i), 
@@ -133,4 +139,4 @@ module DataFifoWrapper
 		.empty		(emptyFlagRx)
 	);
 	
-	endmodule
+endmodule

sources_1/new/DataFifo/FifoCtrl.v

@@ -1,302 +1,263 @@
-module FifoCtrl #(
-    parameter Fifo0ReadMsbAddr		= 12'h0+12'd28,
-	parameter Fifo1ReadMsbAddr		= 12'h50+12'd28,
-	parameter Fifo2ReadMsbAddr		= 12'hf0+12'd28,
-	parameter Fifo3ReadMsbAddr		= 12'h140+12'd28,
-	parameter Fifo4ReadMsbAddr		= 12'h190+12'd28,
-	parameter Fifo5ReadMsbAddr		= 12'h1e0+12'd28,
-	parameter Fifo6ReadMsbAddr		= 12'h230+12'd28,
-    parameter STAGES = 3
-
-
-
-
-)(
-    input ToFifoTxWriteVal_i,
-    input ToFifoTxReadVal_i,
-    input ToFifoRxWriteVal_i,
-    input ToFifoRxReadVal_i,
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     FifoCtrl
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
 
-    input FifoTxFull_i,
-    input FifoTxEmpty_i,
-    input FifoRxFull_i,
-    input FifoRxEmpty_i,
-    input [11:0] SmcAddr_i,
-
-
-    input FifoTxWrClock_i,
-    input FifoTxRdClock_i,
-    input FifoRxWrClock_i,
-    input FifoRxRdClock_i,
+module FifoCtrl #(
+	parameter FIFO_0_READ_MSB_ADDR = 12'h0+12'd28,
+	parameter FIFO_1_READ_MSB_ADDR = 12'h50+12'd28,
+	parameter FIFO_2_READ_MSB_ADDR = 12'hf0+12'd28,
+	parameter FIFO_3_READ_MSB_ADDR = 12'h140+12'd28,
+	parameter FIFO_4_READ_MSB_ADDR = 12'h190+12'd28,
+	parameter FIFO_5_READ_MSB_ADDR = 12'h1e0+12'd28,
+	parameter FIFO_6_READ_MSB_ADDR = 12'h230+12'd28,
+	parameter STAGES = 3
+)
+(
+	input ToFifoTxWriteVal_i,
+	input ToFifoTxReadVal_i,
+	input ToFifoRxWriteVal_i,
+	input ToFifoRxReadVal_i,
 
-    input FifoTxRst_i,
-    input FifoRxRst_i,
+	input FifoTxFull_i,
+	input FifoTxEmpty_i,
+	input FifoRxFull_i,
+	input FifoRxEmpty_i,
+	input [11:0] SmcAddr_i,
 
-    input FifoTxRstWrPtr_i,
-    input FifoRxRstRdPtr_i,
+	input FifoTxWrClock_i,
+	input FifoTxRdClock_i,
+	input FifoRxWrClock_i,
+	input FifoRxRdClock_i,
 
+	input FifoTxRst_i,
+	input FifoRxRst_i,
 
-    output  [7:0] RxFifoUpDnCnt_o,
-    output  [7:0] TxFifoUpDnCnt_o,
+	input FifoTxRstWrPtr_i,
+	input FifoRxRstRdPtr_i,
 
-    output EmptyFlagTxForDsp_o,
+	output [7:0] RxFifoUpDnCnt_o,
+	output [7:0] TxFifoUpDnCnt_o,
 
-    output FifoTxWriteEn_o,
-    output FifoTxReadEn_o,
-    output FifoRxWriteEn_o,
-    output FifoRxReadEn_o
+	output EmptyFlagTxForDsp_o,
 
+	output FifoTxWriteEn_o,
+	output FifoTxReadEn_o,
+	output FifoRxWriteEn_o,
+	output FifoRxReadEn_o
 );
 
+//================================================================================
+//  REG/WIRE
+//================================================================================
+	reg fifoTxWriteEn;
+	reg fifoTxReadEn;
+	reg fifoRxWriteEn;
+	reg fifoRxReadEn;
+	
+	(* dont_touch = "true" *)reg [7:0] txFifoWrPtr;
+	(* dont_touch = "true" *)reg [7:0] txFifoRdPtr;
+	(* dont_touch = "true" *)reg [7:0] rxFifoWrPtr;
+	(* dont_touch = "true" *)reg [7:0] rxFifoRdPtr;
+	
+	(* dont_touch = "true" *)reg [7:0] rxFifoUpDnCnt;
+	(* dont_touch = "true" *)reg [7:0] txFifoUpDnCnt;
+	
+	reg [1:0] readEnCnt;
+	reg emptyFlagTxForDsp;    
+		
+	wire requestToFifo0	= (SmcAddr_i == FIFO_0_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo1	= (SmcAddr_i == FIFO_1_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo2	= (SmcAddr_i == FIFO_2_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo3	= (SmcAddr_i == FIFO_3_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo4	= (SmcAddr_i == FIFO_4_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo5	= (SmcAddr_i == FIFO_5_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	wire requestToFifo6	= (SmcAddr_i == FIFO_6_READ_MSB_ADDR) ? 1'b1 : 1'b0;
+	
+	wire requestToFifo	= (requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6) ? 1'b1 : 1'b0;
 
-    reg fifoTxWriteEn;
-    reg fifoTxReadEn;
-    reg fifoRxWriteEn;
-    reg fifoRxReadEn;
-    
-    (* dont_touch = "true" *)reg [7:0] txFifoWrPtr;
-    (* dont_touch = "true" *)reg [7:0] txFifoRdPtr;
-    (* dont_touch = "true" *)reg [7:0] rxFifoWrPtr;
-    (* dont_touch = "true" *)reg [7:0] rxFifoRdPtr;
-    
-    (* dont_touch = "true" *)reg [7:0] rxFifoUpDnCnt;
-    (* dont_touch = "true" *)reg [7:0] txFifoUpDnCnt;
-    
-    reg [1:0] readEnCnt;
-    reg emptyFlagTxForDsp;    
-    
-    
-    
-    wire	requestToFifo0	=(SmcAddr_i == Fifo0ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo1	=(SmcAddr_i == Fifo1ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo2	=(SmcAddr_i == Fifo2ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo3	=(SmcAddr_i == Fifo3ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo4	=(SmcAddr_i == Fifo4ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo5	=(SmcAddr_i == Fifo5ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo6	=(SmcAddr_i == Fifo6ReadMsbAddr)?1'b1:1'b0;
-    wire	requestToFifo   =(requestToFifo0|requestToFifo1|requestToFifo2|requestToFifo3|requestToFifo4|requestToFifo5|requestToFifo6)?1'b1:1'b0;
-
-    wire [7:0] rxFifoWrPtrSync;
-    wire [7:0] txFifoWrPtrSync;
-    wire [7:0] txFifoRdPtrSync;
-
-    wire rxFifoRstSync;
-
-    
-    
-    
-    // //================================================================================
-    // //	ASSIGNMENTS
-    
-    assign FifoTxWriteEn_o = fifoTxWriteEn;
-    assign FifoTxReadEn_o = fifoTxReadEn;
-    assign FifoRxWriteEn_o = fifoRxWriteEn;
-    assign FifoRxReadEn_o = fifoRxReadEn;
-    
-    
-    assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
-    assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
-    
-
-    assign EmptyFlagTxForDsp_o = emptyFlagTxForDsp;
-    
-    // //================================================================================
-    
-
-    RxFifoPtrSync #(
-        .WIDTH(8),
-        .STAGES(3)
-    )
-    rxFifoPtrSync (
-        .ClkFast_i(FifoRxWrClock_i),
-        .ClkSlow_i(FifoRxRdClock_i),
-        .RxFifoWrPtr_i(rxFifoWrPtr),
-        .RxFifoWrPtr_o(rxFifoWrPtrSync)
-    );
-
-    // TxFifoPtrSync #(
-    //     .WIDTH(8),
-    //     .STAGES(3)
-    // )
-    // txFifoPtrSync (
-    //     .ClkFast_i(FifoTxWrClock_i),
-    //     .ClkSlow_i(FifoTxRdClock_i),
-    //     .TxFifoWrPtr_i(txFifoWrPtr),
-    //     .TxFifoWrPtr_o(txFifoWrPtrSync)
-    // );
-
-    // RxFifoRstSync #(
-    //     .WIDTH(1),
-    //     .STAGES(3)
-    // )
-    // rxFifoRstSync (
-    //     .ClkFast_i(FifoRxWrClock_i),
-    //     .ClkSlow_i(FifoRxRdClock_i),
-    //     .RxFifoRst_i(FifoRxRst_i),
-    //     .RxFifoRst_o(rxFifoRstSync)
-    // );
-
-
-    TxFifoPtrSync #(
-        .WIDTH(8),
-        .STAGES(3)
-    )
-    txFifoPtrSync (
-        .ClkFast_i(FifoTxRdClock_i),
-        .ClkSlow_i(FifoTxWrClock_i),
-        .TxFifoWrPtr_i(txFifoRdPtr),
-        .TxFifoWrPtr_o(txFifoRdPtrSync)
-    );
+	wire [7:0] rxFifoWrPtrSync;
+	wire [7:0] txFifoWrPtrSync;
+	wire [7:0] txFifoRdPtrSync;
 
-    
-    always @(posedge FifoRxRdClock_i) begin 
-        if (FifoRxRstRdPtr_i) begin 
-            readEnCnt <= 1'b0;
-        end
-        else begin 
-            if (ToFifoRxReadVal_i) begin 
-                readEnCnt <= readEnCnt + 1'b1;
-            end
-            else begin 
-                readEnCnt <= 1'b0;
-            end
-        end
-    end
-    
-    
-    
-    always @(posedge FifoTxWrClock_i) begin 
-        if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
-            fifoTxWriteEn <= 1'b1;
-        end
-        else begin 
-            fifoTxWriteEn <= 1'b0;
-        end
-    end
-    
-    
-    always @(posedge FifoTxRdClock_i ) begin 
-        if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
-            fifoTxReadEn <= 1'b1;
-        end
-        else begin 
-            fifoTxReadEn <= 1'b0;
-        end
-    end
-    
-    
-    always @(posedge FifoRxWrClock_i) begin 
-        if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
-            fifoRxWriteEn <= 1'b1;
-        end
-        else begin 
-            fifoRxWriteEn <= 1'b0;
-        end
-    end
-    
-    
-    always @(posedge FifoRxRdClock_i) begin 
-        if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
-            fifoRxReadEn <= 1'b1;
-        end
-        else begin 
-            fifoRxReadEn <= 1'b0;
-        end
-    end
-    
-    
-    always @(posedge FifoTxWrClock_i ) begin 
-        if (FifoTxRstWrPtr_i) begin 
-            txFifoWrPtr <= 8'h0;
-        end
-        else begin 
-            if (fifoTxWriteEn  ) begin 
-                txFifoWrPtr <= txFifoWrPtr + 1'b1;
-            end
-        end
-    end
-    
-    always @(posedge FifoTxRdClock_i ) begin 
-        if (FifoTxRst_i) begin 
-            txFifoRdPtr <= 8'h0;
-        end
-        else begin 
-            if (fifoTxReadEn ) begin 
-                txFifoRdPtr <= txFifoRdPtr + 1'b1;
-            end
-        end
-    end
-    
-    
-    always @(posedge FifoRxWrClock_i) begin 
-        if (FifoRxRst_i) begin 
-            rxFifoWrPtr <= 8'h0;
-        end
-        else begin
-            if (fifoRxWriteEn ) begin 
-                rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
-            end
-        end
-    end
-    
-    always @(posedge FifoRxRdClock_i) begin 
-        if (FifoRxRstRdPtr_i) begin 
-            rxFifoRdPtr <= 8'h0;
-        end
-        else begin 
-            if (fifoRxReadEn ) begin 
-                rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
-            end
-        end
-    end
-    
-    
-    always @(posedge FifoRxRdClock_i) begin 
-        if (FifoRxRstRdPtr_i) begin 
-            rxFifoUpDnCnt <= 8'h0;
-        end
-        else begin 
-            rxFifoUpDnCnt <= rxFifoWrPtrSync - rxFifoRdPtr;
-        end
-    end
-    
-    always @(posedge FifoTxWrClock_i) begin 
-        if (FifoTxRst_i) begin 
-            txFifoUpDnCnt <= 8'h0;
-        end
-        else begin 
-            txFifoUpDnCnt <= txFifoWrPtr - txFifoRdPtrSync;
-        end
-    end
-    
-    
-    // always @(posedge FifoTxWrClock_i) begin 
-    //     if (FifoTxRstWrPtr_i) begin 
-    //         emptyFlagTxForDsp <= 1'b1;
-    //     end
-    //     else begin 
-    //         if (txFifoWrPtr == txFifoRdPtr) begin 
-    //             emptyFlagTxForDsp <= 1'b1;
-    //         end
-    //         else begin 
-    //             emptyFlagTxForDsp <= 1'b0;
-    //         end
-    //     end
-    // end
+	wire rxFifoRstSync;
 
-    always @(*) begin
-        if (txFifoUpDnCnt == 8'h0) begin
-            emptyFlagTxForDsp <= 1'b1;
-        end
-        else begin
-            emptyFlagTxForDsp <= 1'b0;
-        end
-    end
+//================================================================================
+//	ASSIGNMENTS
+//================================================================================	
+	assign FifoTxWriteEn_o = fifoTxWriteEn;
+	assign FifoTxReadEn_o = fifoTxReadEn;
+	assign FifoRxWriteEn_o = fifoRxWriteEn;
+	assign FifoRxReadEn_o = fifoRxReadEn;
+	
+	assign RxFifoUpDnCnt_o = rxFifoUpDnCnt;
+	assign TxFifoUpDnCnt_o = txFifoUpDnCnt;
+	
+	assign EmptyFlagTxForDsp_o = emptyFlagTxForDsp;
+	
+//================================================================================
+//	LOCALPARAMS
+//================================================================================
 
+//================================================================================
+//	CODING
+//================================================================================
+	RxFifoPtrSync #(
+		.WIDTH	(8),
+		.STAGES	(STAGES)
+	)
+	rxFifoPtrSync (
+		.ClkFast_i		(FifoRxWrClock_i),
+		.ClkSlow_i		(FifoRxRdClock_i),
+		.RxFifoWrPtr_i	(rxFifoWrPtr),
+		.RxFifoWrPtr_o	(rxFifoWrPtrSync)
+	);
 
+	TxFifoPtrSync #(
+		.WIDTH	(8),
+		.STAGES	(STAGES)
+	)
+	txFifoPtrSync (
+		.ClkFast_i(FifoTxRdClock_i),
+		.ClkSlow_i(FifoTxWrClock_i),
+		.TxFifoWrPtr_i(txFifoRdPtr),
+		.TxFifoWrPtr_o(txFifoRdPtrSync)
+	);
+	
+	always @(posedge FifoRxRdClock_i) begin 
+		if (FifoRxRstRdPtr_i) begin 
+			readEnCnt <= 1'b0;
+		end
+		else begin 
+			if (ToFifoRxReadVal_i) begin 
+				readEnCnt <= readEnCnt + 1'b1;
+			end
+			else begin 
+				readEnCnt <= 1'b0;
+			end
+		end
+	end
+	
+	always @(posedge FifoTxWrClock_i) begin 
+		if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
+			fifoTxWriteEn <= 1'b1;
+		end
+		else begin 
+			fifoTxWriteEn <= 1'b0;
+		end
+	end
+	
+	always @(posedge FifoTxRdClock_i) begin 
+		if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
+			fifoTxReadEn <= 1'b1;
+		end
+		else begin 
+			fifoTxReadEn <= 1'b0;
+		end
+	end
+	
+	always @(posedge FifoRxWrClock_i) begin 
+		if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
+			fifoRxWriteEn <= 1'b1;
+		end
+		else begin 
+			fifoRxWriteEn <= 1'b0;
+		end
+	end
+	
+	always @(posedge FifoRxRdClock_i) begin 
+		if (ToFifoRxReadVal_i && !FifoRxEmpty_i && requestToFifo && readEnCnt < 1 ) begin 
+			fifoRxReadEn <= 1'b1;
+		end
+		else begin 
+			fifoRxReadEn <= 1'b0;
+		end
+	end
+	
+	always @(posedge FifoTxWrClock_i) begin 
+		if (FifoTxRstWrPtr_i) begin 
+			txFifoWrPtr <= 8'h0;
+		end
+		else begin 
+			if (fifoTxWriteEn  ) begin 
+				txFifoWrPtr <= txFifoWrPtr + 1'b1;
+			end
+		end
+	end
+	
+	always @(posedge FifoTxRdClock_i) begin 
+		if (FifoTxRst_i) begin 
+			txFifoRdPtr <= 8'h0;
+		end
+		else begin 
+			if (fifoTxReadEn) begin 
+				txFifoRdPtr <= txFifoRdPtr + 1'b1;
+			end
+		end
+	end
+	
+	always @(posedge FifoRxWrClock_i) begin 
+		if (FifoRxRst_i) begin 
+			rxFifoWrPtr <= 8'h0;
+		end
+		else begin
+			if (fifoRxWriteEn) begin 
+				rxFifoWrPtr <= rxFifoWrPtr + 1'b1;
+			end
+		end
+	end
+	
+	always @(posedge FifoRxRdClock_i) begin 
+		if (FifoRxRstRdPtr_i) begin 
+			rxFifoRdPtr <= 8'h0;
+		end
+		else begin 
+			if (fifoRxReadEn) begin 
+				rxFifoRdPtr <= rxFifoRdPtr + 1'b1;
+			end
+		end
+	end
+	
+	always @(posedge FifoRxRdClock_i) begin 
+		if (FifoRxRstRdPtr_i) begin 
+			rxFifoUpDnCnt <= 8'h0;
+		end
+		else begin 
+			rxFifoUpDnCnt <= rxFifoWrPtrSync - rxFifoRdPtr;
+		end
+	end
+	
+	always @(posedge FifoTxWrClock_i) begin 
+		if (FifoTxRst_i) begin 
+			txFifoUpDnCnt <= 8'h0;
+		end
+		else begin 
+			txFifoUpDnCnt <= txFifoWrPtr - txFifoRdPtrSync;
+		end
+	end
 
-    
-    
-    // //================================================================================
-    
-    endmodule
+	always @(*) begin
+		if (txFifoUpDnCnt == 8'h0) begin
+			emptyFlagTxForDsp <= 1'b1;
+		end
+		else begin
+			emptyFlagTxForDsp <= 1'b0;
+		end
+	end
+	
+endmodule

sources_1/new/DataFifo/RxFifoPtrSync.v

@@ -1,9 +1,26 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     RxFifoPtrSync
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
 module RxFifoPtrSync #(
     parameter WIDTH = 8,
     parameter STAGES = 3
-
-
-
 )
 (
     input ClkFast_i,
@@ -13,35 +30,33 @@ module RxFifoPtrSync #(
     output [WIDTH-1:0] RxFifoWrPtr_o
 );
 
-
-
-
+//================================================================================
+//  REG/WIRE
+//================================================================================
 //lauch registers 
 reg [WIDTH-1:0] rxFifoWrPtrReg;
 
-
 // capture registers
 (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoWrPtrReg_c;
 
-
-
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
 assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
 
+//================================================================================
+//  CODING
+//================================================================================
 always @(posedge ClkFast_i) begin
     rxFifoWrPtrReg <= RxFifoWrPtr_i;
 end
 
-
-
-
-
 always @(posedge ClkSlow_i) begin
     rxFifoWrPtrReg_c <= {rxFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], rxFifoWrPtrReg};
 end
 
-
-
-
-
 endmodule

sources_1/new/DataFifo/RxFifoRstSync.v

@@ -1,9 +1,26 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     RxFifoRstSync
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
 module RxFifoRstSync #(
     parameter WIDTH = 1,
     parameter STAGES = 3
-
-
-
 )
 (
     input ClkFast_i,
@@ -13,33 +30,33 @@ module RxFifoRstSync #(
     output [WIDTH-1:0] RxFifoRst_o
 );
 
-
-
-
-
+//================================================================================
+//  REG/WIRE
+//================================================================================
 //lauch registers 
 reg [WIDTH-1:0] rxFifoRstReg;
 
-
 // capture registers
 (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoRstReg_c;
 
-
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
 assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
 
-
+//================================================================================
+//  CODING
+//================================================================================
 always @(posedge ClkFast_i) begin
     rxFifoRstReg <= RxFifoRst_i;
 end
 
-
 always @(posedge ClkSlow_i) begin
     rxFifoRstReg_c <= {rxFifoRstReg_c[(STAGES-1)*WIDTH-1:0], rxFifoRstReg};
 end
 
-
-
-
-
 endmodule

sources_1/new/DataFifo/TxFifoPtrsync.v

@@ -1,9 +1,26 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        
+// 
+// Create Date:     10/30/2023 11:24:31 AM
+// Design Name:
+// Module Name:     TxFifoPtrSync
+// Project Name:    S5443_V3_FPGA3
+// Target Devices:  BOARD: BY5443v3. FPGA: xc7s25csga225-2
+// Tool Versions:
+// Description:     
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 1.0 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
 module TxFifoPtrSync #(
     parameter WIDTH = 8,
     parameter STAGES = 3
-
-
-
 )
 (
     input ClkFast_i,
@@ -13,32 +30,33 @@ module TxFifoPtrSync #(
     output [WIDTH-1:0] TxFifoWrPtr_o
 );
 
+//================================================================================
+//  REG/WIRE
+//================================================================================
 //lauch registers 
 reg [WIDTH-1:0] txFifoWrPtrReg;
 
-
 // capture registers
 (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] txFifoWrPtrReg_c;
 
-
-
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
 assign TxFifoWrPtr_o = txFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
 
+//================================================================================
+//  LOCALPARAMS
+//================================================================================
 
+//================================================================================
+//  CODING
+//================================================================================
 always @(posedge ClkFast_i) begin
     txFifoWrPtrReg <= TxFifoWrPtr_i;
 end
 
-
-
-
-
 always @(posedge ClkSlow_i) begin
     txFifoWrPtrReg_c <= {txFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], txFifoWrPtrReg};
 end
 
-
-
-
-
 endmodule

sources_1/new/S5443_3Top.v

@@ -723,7 +723,8 @@ module S5443_3Top
 				.STAGES(STAGES),
 				.CMD_REG_WIDTH(CmdRegWidth),
 				.ADDR_REG_WIDTH(AddrRegWidth),
-				.WIDTH(1)
+				.WIDTH(1),
+				.FIFO_NUM(SpiNum)
 			) SpiSubSystem(
 				.Clk123_i(gclk),
 				.SpiClk_i(spiClkBus[i]),

sources_1/new/SpiSubSystem/SpiSubSystem.v

@@ -22,7 +22,8 @@ module SpiSubSystem #(
 	parameter STAGES = 3,
 	parameter CMD_REG_WIDTH = 32,
 	parameter ADDR_REG_WIDTH = 12,
-	parameter WIDTH  = 1 
+	parameter WIDTH  = 1,
+    parameter FIFO_NUM = 7
 ) 
 (
 	input Clk123_i,
@@ -119,7 +120,10 @@ Sync1bit #(
 );
 
 DataFifoWrapper #(
-	.STAGES				(STAGES)
+	.CMD_REG_WIDTH		(CMD_REG_WIDTH),
+	.ADDR_REG_WIDTH		(ADDR_REG_WIDTH),
+	.STAGES				(STAGES),
+	.FIFO_NUM			(FIFO_NUM)
 ) DataFifoWrapper
 (
 	.WrClk_i			(Clk123_i),