Добавлены SPIm, SPIs, логика выбора типа SPI

SRAM/QuadSPIm.v

@@ -20,7 +20,7 @@ module QuadSPIm(
     output reg Mosi2_i,
     output reg Mosi3_i,
     output reg  Sck_o,
-    output reg Val_o,
+    output  Val_o,
     output Ss_o
 
 );
@@ -28,6 +28,10 @@ module QuadSPIm(
 //  REG/WIRE
 //================================================================================
 reg startFlag;
+reg startR;
+reg [31:0] trCnt;
+reg valReg;
+reg valToRxFifo1;
 reg [2:0] ssCnt;
 reg Ss;
 reg SSr;
@@ -46,11 +50,41 @@ wire SsPol = SELST_i ? Ss : ~Ss;
 //================================================================================
 
 assign Ss_o = SsPol; 
-
+assign Val_o = (trCnt < 1 ) ?valToRxFifo1:valReg;
 //================================================================================
 //  CODING
 //================================================================================	
 
+always @(posedge Clk_i) begin 
+    startR <= Start_i;
+end
+
+always @(*) begin 
+    if (Rst_i) begin 
+        valToRxFifo1 = 1'b0;
+    end
+    else begin 
+        if (Start_i && !startR) begin 
+            valToRxFifo1 = 1'b1;
+        end
+        else begin 
+            valToRxFifo1 = 1'b0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        trCnt <= 1'b0;
+    end
+    else begin 
+        if ( (ssNum + LEAD_i + LAG_i)-1) begin 
+            trCnt <= trCnt + 1'b1;
+        end
+    end
+end
+
+
 
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
@@ -240,18 +274,18 @@ end
 always @(*) begin
     if (SELST_i) begin 
         if (Ss && !SSr) begin 
-            Val_o = 1'b1;
+            valReg = 1'b1;
         end
         else begin 
-            Val_o = 1'b0;
+            valReg = 1'b0;
         end
     end
     else begin 
         if (!Ss&& SSr) begin 
-            Val_o = 1'b1;
+            valReg = 1'b1;
         end
         else begin 
-            Val_o = 1'b0;
+            valReg = 1'b0;
         end
     end
 end

SRAM/RegMap.v

@@ -239,73 +239,73 @@ assign Led_o = LedReg[0];
 //	LOCALPARAMS
 //================================================================================
 localparam Spi0CtrlAddr = 12'h00;
-localparam Spi0ClkAddr  = 12'h04;
-localparam Spi0CsDelayAddr = 12'h08;
-localparam Spi0CsCtrlAddr = 12'h0c;
-localparam Spi0TxFifoCtrlAddr = 12'h10;
-localparam Spi0RxFifoCtrlAddr = 12'h14;
-localparam Spi0TxFifo = 12'h18;
-localparam Spi0RxFifo = 12'h1c;
+localparam Spi0ClkAddr  = 12'h08;
+localparam Spi0CsDelayAddr = 12'h10;
+localparam Spi0CsCtrlAddr = 12'h18;
+localparam Spi0TxFifoCtrlAddr = 12'h20;
+localparam Spi0RxFifoCtrlAddr = 12'h28;
+localparam Spi0TxFifo = 12'h30;
+localparam Spi0RxFifo = 12'h38;
 
-localparam Spi1CtrlAddr = 12'h50;
-localparam Spi1ClkAddr  = 12'h54;
-localparam Spi1CsDelayAddr = 12'h58;
-localparam Spi1CsCtrlAddr = 12'h5c;
-localparam Spi1TxFifoCtrlAddr = 12'h60;
-localparam Spi1RxFifoCtrlAddr = 12'h64;
-localparam Spi1TxFifo = 12'h68;
-localparam Spi1RxFifo = 12'h6c;
+localparam Spi1CtrlAddr = 12'hA0;
+localparam Spi1ClkAddr  = 12'hA8;
+localparam Spi1CsDelayAddr = 12'hB0;
+localparam Spi1CsCtrlAddr = 12'hB8;
+localparam Spi1TxFifoCtrlAddr = 12'hC0;
+localparam Spi1RxFifoCtrlAddr = 12'hC8;
+localparam Spi1TxFifo = 12'hD0;
+localparam Spi1RxFifo = 12'hD8;
 
-localparam Spi2CtrlAddr = 12'hF0;
-localparam Spi2ClkAddr  = 12'hF4;
-localparam Spi2CsDelayAddr = 12'hF8;
-localparam Spi2CsCtrlAddr = 12'hFc;
-localparam Spi2TxFifoCtrlAddr = 12'h100;
-localparam Spi2RxFifoCtrlAddr = 12'h104;
-localparam Spi2TxFifo = 12'h108;
-localparam Spi2RxFifo = 12'h10c;
+localparam Spi2CtrlAddr = 12'h1E0;
+localparam Spi2ClkAddr  = 12'h1E8;
+localparam Spi2CsDelayAddr = 12'h1F0;
+localparam Spi2CsCtrlAddr = 12'h1F8;
+localparam Spi2TxFifoCtrlAddr = 12'h200;
+localparam Spi2RxFifoCtrlAddr = 12'h208;
+localparam Spi2TxFifo = 12'h210;
+localparam Spi2RxFifo = 12'h218;
 
-localparam Spi3CtrlAddr = 12'h140;
-localparam Spi3ClkAddr  = 12'h144;
-localparam Spi3CsDelayAddr = 12'h148;
-localparam Spi3CsCtrlAddr = 12'h14c;
-localparam Spi3TxFifoCtrlAddr = 12'h150;
-localparam Spi3RxFifoCtrlAddr = 12'h154;
-localparam Spi3TxFifo = 12'h158;
-localparam Spi3RxFifo = 12'h15c;
+localparam Spi3CtrlAddr = 12'h280;
+localparam Spi3ClkAddr  = 12'h288;
+localparam Spi3CsDelayAddr = 12'h290;
+localparam Spi3CsCtrlAddr = 12'h298;
+localparam Spi3TxFifoCtrlAddr = 12'h2A0;
+localparam Spi3RxFifoCtrlAddr = 12'h2A8;
+localparam Spi3TxFifo = 12'h2B0;
+localparam Spi3RxFifo = 12'h2B8;
 
-localparam Spi4CtrlAddr = 12'h190;
-localparam Spi4ClkAddr  = 12'h194;
-localparam Spi4CsDelayAddr = 12'h198;
-localparam Spi4CsCtrlAddr = 12'h19c;
-localparam Spi4TxFifoCtrlAddr = 12'h1a0;
-localparam Spi4RxFifoCtrlAddr = 12'h1a4;
-localparam Spi4TxFifo = 12'h1a8;
-localparam Spi4RxFifo = 12'h1ac;
+localparam Spi4CtrlAddr = 12'h320;
+localparam Spi4ClkAddr  = 12'h328;
+localparam Spi4CsDelayAddr = 12'h330;
+localparam Spi4CsCtrlAddr = 12'h338;
+localparam Spi4TxFifoCtrlAddr = 12'h340;
+localparam Spi4RxFifoCtrlAddr = 12'h348;
+localparam Spi4TxFifo = 12'h350;
+localparam Spi4RxFifo = 12'h358;
 
-localparam Spi5CtrlAddr = 12'h1e0;
-localparam Spi5ClkAddr  = 12'h1e4;
-localparam Spi5CsDelayAddr = 12'h1e8;
-localparam Spi5CsCtrlAddr = 12'h1ec;
-localparam Spi5TxFifoCtrlAddr = 12'h1f0;
-localparam Spi5RxFifoCtrlAddr = 12'h1f4;
-localparam Spi5TxFifo = 12'h1f8;
-localparam Spi5RxFifo = 12'h1fc;
+localparam Spi5CtrlAddr = 12'h3C0;
+localparam Spi5ClkAddr  = 12'h3C8;
+localparam Spi5CsDelayAddr = 12'h3D0;
+localparam Spi5CsCtrlAddr = 12'h3D8;
+localparam Spi5TxFifoCtrlAddr = 12'h3E0;
+localparam Spi5RxFifoCtrlAddr = 12'h3E8;
+localparam Spi5TxFifo = 12'h3F0;
+localparam Spi5RxFifo = 12'h3F8;
 
-localparam Spi6CtrlAddr = 12'h230;
-localparam Spi6ClkAddr  = 12'h234;
-localparam Spi6CsDelayAddr = 12'h238;
-localparam Spi6CsCtrlAddr = 12'h23c;
-localparam Spi6TxFifoCtrlAddr = 12'h240;
-localparam Spi6RxFifoCtrlAddr = 12'h244;
-localparam Spi6TxFifo = 12'h248;
-localparam Spi6RxFifo = 12'h24c;
+localparam Spi6CtrlAddr = 12'h460;
+localparam Spi6ClkAddr  = 12'h468;
+localparam Spi6CsDelayAddr = 12'h470;
+localparam Spi6CsCtrlAddr = 12'h478;
+localparam Spi6TxFifoCtrlAddr = 12'h480;
+localparam Spi6RxFifoCtrlAddr = 12'h488;
+localparam Spi6TxFifo = 12'h490;
+localparam Spi6RxFifo = 12'h498;
 
-localparam SpiTxRxEn = 12'hF00;
-localparam GPIOCtrlAddr = 12'hFF0;
+localparam SpiTxRxEn = 12'h1E00;
+localparam GPIOCtrlAddr = 12'h1FE0;
 
-localparam Debug0Addr = 12'hFF8;
-localparam Debug1Addr = 12'hFFC;
+localparam Debug0Addr = 12'h1FF0;
+localparam Debug1Addr = 12'h1FF8;
 //================================================================================
 
 

constrs_1/new/S5443_3.xdc

@@ -95,12 +95,12 @@ set_property PACKAGE_PIN J3 [get_ports {Mosi1_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[0]}]
 set_property PACKAGE_PIN H2 [get_ports {Mosi2_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}]
-set_property PACKAGE_PIN L1  [get_ports {Mosi3_o[0]}]
+set_property PACKAGE_PIN L1 [get_ports {Mosi3_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}]
 set_property PACKAGE_PIN J2 [get_ports {SpiRst_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[0]}]
-set_property PACKAGE_PIN M13 [get_ports {LD_i[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[0]}]
+set_property PACKAGE_PIN M13 [get_ports {Ld_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[0]}]
 
 
 
@@ -121,8 +121,8 @@ set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[1]}]
 set_property PACKAGE_PIN P2 [get_ports {SpiRst_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[1]}]
-set_property PACKAGE_PIN N11 [get_ports {LD_i[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[1]}]
+set_property PACKAGE_PIN N11 [get_ports {Ld_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[1]}]
 
 
 
@@ -143,8 +143,8 @@ set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[2]}]
 set_property PACKAGE_PIN E3 [get_ports {SpiRst_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[2]}]
-set_property PACKAGE_PIN N9 [get_ports {LD_i[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[2]}]
+set_property PACKAGE_PIN N9 [get_ports {Ld_i[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[2]}]
 
 
 #SPI3
@@ -164,8 +164,8 @@ set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[3]}]
 set_property PACKAGE_PIN R9 [get_ports {SpiRst_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[3]}]
-set_property PACKAGE_PIN N13 [get_ports {LD_i[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[3]}]
+set_property PACKAGE_PIN N13 [get_ports {Ld_i[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[3]}]
 
 
 
@@ -187,8 +187,8 @@ set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[4]}]
 set_property PACKAGE_PIN N15 [get_ports {SpiRst_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[4]}]
-set_property PACKAGE_PIN P15 [get_ports {LD_i[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[4]}]
+set_property PACKAGE_PIN P15 [get_ports {Ld_i[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[4]}]
 
 
 
@@ -209,8 +209,8 @@ set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]
 set_property PACKAGE_PIN N6 [get_ports {SpiRst_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[5]}]
-set_property PACKAGE_PIN N12 [get_ports {LD_i[5]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[5]}]
+set_property PACKAGE_PIN N12 [get_ports {Ld_i[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[5]}]
 
 
 #SPI6
@@ -230,8 +230,8 @@ set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[6]}]
 set_property PACKAGE_PIN A2 [get_ports {SpiRst_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[6]}]
-set_property PACKAGE_PIN M8 [get_ports {LD_i[6]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[6]}]
+set_property PACKAGE_PIN M8 [get_ports {Ld_i[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[6]}]
 
 
 set_property PACKAGE_PIN M7 [get_ports LD_o]
@@ -268,3 +268,38 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
 
 
 
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list gclk]]
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
+set_property port_width 7 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {Ss_o_OBUF[0]} {Ss_o_OBUF[1]} {Ss_o_OBUF[2]} {Ss_o_OBUF[3]} {Ss_o_OBUF[4]} {Ss_o_OBUF[5]} {Ss_o_OBUF[6]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
+set_property port_width 16 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {SmcData_i_IBUF[0]} {SmcData_i_IBUF[1]} {SmcData_i_IBUF[2]} {SmcData_i_IBUF[3]} {SmcData_i_IBUF[4]} {SmcData_i_IBUF[5]} {SmcData_i_IBUF[6]} {SmcData_i_IBUF[7]} {SmcData_i_IBUF[8]} {SmcData_i_IBUF[9]} {SmcData_i_IBUF[10]} {SmcData_i_IBUF[11]} {SmcData_i_IBUF[12]} {SmcData_i_IBUF[13]} {SmcData_i_IBUF[14]} {SmcData_i_IBUF[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
+set_property port_width 11 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {SmcAddr_i_IBUF[0]} {SmcAddr_i_IBUF[1]} {SmcAddr_i_IBUF[2]} {SmcAddr_i_IBUF[3]} {SmcAddr_i_IBUF[4]} {SmcAddr_i_IBUF[5]} {SmcAddr_i_IBUF[6]} {SmcAddr_i_IBUF[7]} {SmcAddr_i_IBUF[8]} {SmcAddr_i_IBUF[9]} {SmcAddr_i_IBUF[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 1 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list SmcAre_i_IBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list SmcAwe_i_IBUF]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets gclk]

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -21,7 +21,8 @@ module DataFifoWrapper
 	input ToFifoTxReadVal_i,
 
 	output	ToSpiVal_o,
-	output	[CmdRegWidth-1:0]	ToSpiData_o
+	output	[CmdRegWidth-1:0]	ToSpiData_o,
+	output  [CmdRegWidth-1:0]   DataFromRxFifo_o
 );
 //================================================================================
 //	REG/WIRE

sources_1/new/S5443_3Top.v

@@ -189,6 +189,7 @@ wire [SpiNum-1:0] valToTxFifoRead;
 wire [SpiNum-1:0] SckR; 
 wire [SpiNum-1:0] SsR;
 wire [SpiNum-1:0] Mosi0R;
+wire [SpiNum-1:0] valReg;
 wire [SpiNum-1:0] valToTxR;
 wire [SpiNum-1:0] valToRxR;
 wire [0:31] dataToRxFifoR [SpiNum-1:0];
@@ -200,6 +201,9 @@ wire [SpiNum-1:0] Mosi0Q;
 wire [SpiNum-1:0] valToTxQ;
 wire [SpiNum-1:0] valToRxQ;
 wire [0:31] dataToRxFifoQ [SpiNum-1:0];
+wire [0:15] dataFromRxFifo [SpiNum-1:0];
+reg  [15:0] dataFromRxFifoR;
+wire [15:0] dataFromRxFifoW;
 
 
 
@@ -212,9 +216,8 @@ wire [0:31] dataToRxFifoQ [SpiNum-1:0];
 //  ASSIGNMENTS
 //================================================================================
 assign addr = {SmcAddr_i, 1'b0};
-assign Data_i = (!SmcAoe_i) ? data : 16'bz;
+assign Data_i = (!SmcAre_i) ? dataFromRxFifoW : 16'bz;
 assign ten = SpiTxRxEn[6:0];
-assign Mosi0_o = Mosi0;
 assign Mosi1_o = Mosi1;
 assign Mosi2_o = Mosi2;
 assign Mosi3_o = Mosi3;
@@ -407,13 +410,13 @@ assign Sck[4] = (spiMode)? SckQ[4]:SckR[4];
 assign Sck[5] = (spiMode)? SckQ[5]:SckR[5];
 assign Sck[6] = (spiMode)? SckQ[6]:SckR[6];
 
-assign Mosi0[0] = (spiMode)? Mosi0Q[0]:Mosi0R[0];
-assign Mosi0[1] = (spiMode)? Mosi0Q[1]:Mosi0R[1];
-assign Mosi0[2] = (spiMode)? Mosi0Q[2]:Mosi0R[2];
-assign Mosi0[3] = (spiMode)? Mosi0Q[3]:Mosi0R[3];
-assign Mosi0[4] = (spiMode)? Mosi0Q[4]:Mosi0R[4];
-assign Mosi0[5] = (spiMode)? Mosi0Q[5]:Mosi0R[5];
-assign Mosi0[6] = (spiMode)? Mosi0Q[6]:Mosi0R[6];
+assign Mosi0[0] = (spiMode)? Mosi0Q[0]:valReg[0];
+assign Mosi0[1] = (spiMode)? Mosi0Q[1]:valReg[1];
+assign Mosi0[2] = (spiMode)? Mosi0Q[2]:valReg[2];
+assign Mosi0[3] = (spiMode)? Mosi0Q[3]:valReg[3];
+assign Mosi0[4] = (spiMode)? Mosi0Q[4]:valReg[4];
+assign Mosi0[5] = (spiMode)? Mosi0Q[5]:valReg[5];
+assign Mosi0[6] = (spiMode)? Mosi0Q[6]:valReg[6];
 
 assign valToTxFifoRead[0] = (spiMode)? valToTxQ[0]:valToTxR[0];
 assign valToTxFifoRead[1] = (spiMode)? valToTxQ[1]:valToTxR[1];
@@ -440,12 +443,46 @@ assign dataToRxFifo[5] = (spiMode)? dataToRxFifoQ[5]:dataToRxFifoR[5];
 assign dataToRxFifo[6] = (spiMode)? dataToRxFifoQ[6]:dataToRxFifoR[6];
 
 
-
+assign dataFromRxFifoW =  dataFromRxFifoR;
 
 //================================================================================
 //  CODING
 //================================================================================	
 
+always @(*) begin 
+    if (initRst) begin 
+        dataFromRxFifoR = 16'b0;
+    end
+    else begin 
+        case (Ss_o)  
+            7'b0000001: begin 
+                dataFromRxFifoR = dataFromRxFifo[0];
+            end
+            7'b0000010: begin 
+                dataFromRxFifoR = dataFromRxFifo[1];
+            end
+            7'b0000011: begin 
+                dataFromRxFifoR = dataFromRxFifo[2];
+            end
+            7'b0000100: begin 
+                dataFromRxFifoR = dataFromRxFifo[3];
+            end
+            7'b0000101: begin 
+                dataFromRxFifoR = dataFromRxFifo[4];
+            end
+            7'b0000110: begin 
+                dataFromRxFifoR = dataFromRxFifo[5];
+            end
+            7'b0000111: begin 
+                dataFromRxFifoR = dataFromRxFifo[6];
+            end
+            default: dataFromRxFifoR = 16'b0;
+        endcase
+    end
+end
+
+
+
 BUFG BUFG_inst (
    .O(gclk), // 1-bit output: Clock output
    .I(Clk123_i)  // 1-bit input: Clock input
@@ -611,6 +648,7 @@ generate
 
 			
 			.ToSpiVal_o		(toSpiVal[i]),
+            .DataFromRxFifo_o (dataToRxFifo[i]),
 			.ToSpiData_o	(toSpiData[i])
 		);
 
@@ -623,7 +661,7 @@ generate
             .SPIdata(toSpiData[i]),
             .Sck_o(SckR[i]),
             .Ss_o(SsR[i]),
-            .Mosi0_o(Mosi0R[i]),
+            .Mosi0_o(valReg[i]),
             .WidthSel_i(widthSel[i]),
             .PulsePol_i(CPOL[i]),
             .CPHA_i(CPHA[i]),
@@ -647,7 +685,7 @@ generate
             .Rst_i(initRst|SpiRst_o[i]| spiMode[i]),
             .Sck_i(SckR[i]),
             .Ss_i(SsR[i]),
-            .Mosi0_i(Mosi0R[i]),
+            .Mosi0_i(valReg[i]),
             .WidthSel_i(widthSel[i]),
             .SELST_i(selSt[i]),
             .DataToRxFifo_o(dataToRxFifoR[i]),
@@ -662,9 +700,9 @@ generate
 			.SpiDataVal_i	(toSpiVal),
             // .SPIdata(32'h2aaa00aa),
             .SPIdata(toSpiData[i]),
-            .Sck_o(Sck[i]),
-            .Ss_o(Ss[i]),
-            .Mosi0_i(Mosi0[i]),
+            .Sck_o(SckQ[i]),
+            .Ss_o(SsQ[i]),
+            .Mosi0_i(Mosi0Q[i]),
             .Mosi1_i(Mosi1[i]),
             .Mosi2_i(Mosi2[i]),
             .Mosi3_i(Mosi3[i]),
@@ -681,8 +719,8 @@ generate
         QuadSPIs QuadSPIs_inst (
             .Clk_i(spiClkBus[i]),
             .Rst_i(initRst|SpiRst_o[i]| !spiMode[i]),
-            .Sck_i(Sck[i]),
-            .Ss_i(Ss[i]),
+            .Sck_i(SckQ[i]),
+            .Ss_i(SsQ[i]),
             .Mosi0_i(Mosi0[i]),
             .Mosi1_i(Mosi1[i]),
             .Mosi2_i(Mosi2[i]),

sources_1/new/SpiR/SPIm.v

@@ -17,7 +17,7 @@ module SPIm (
     output reg Mosi0_o,
     output reg Sck_o,
     output  Ss_o,
-    output reg Val_o
+    output  Val_o
 );
 
 
@@ -26,6 +26,10 @@ module SPIm (
 //================================================================================
 
 reg startFlag;
+reg startR;
+reg [31:0] trCnt;
+reg valReg;
+reg valToRxFifo1;
 reg [2:0] ssCnt;
 reg Ss;
 reg SSr;
@@ -46,10 +50,38 @@ assign Ss_o = SsPol;
 
 
 
-
+assign Val_o = (trCnt < 1 ) ?valToRxFifo1:valReg;
 //================================================================================
 //	CODING
 //================================================================================
+always @(posedge Clk_i) begin 
+    startR <= Start_i;
+end
+
+always @(*) begin 
+    if (Rst_i) begin 
+        valToRxFifo1 = 1'b0;
+    end
+    else begin 
+        if (Start_i && !startR) begin 
+            valToRxFifo1 = 1'b1;
+        end
+        else begin 
+            valToRxFifo1 = 1'b0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        trCnt <= 1'b0;
+    end
+    else begin 
+        if ( (ssNum + LEAD_i + LAG_i)-1) begin 
+            trCnt <= trCnt + 1'b1;
+        end
+    end
+end
 
 
 
@@ -239,18 +271,18 @@ end
 always @(*) begin
     if (SELST_i) begin 
         if (Ss && !SSr) begin 
-            Val_o = 1'b1;
+            valReg = 1'b1;
         end
         else begin 
-            Val_o = 1'b0;
+            valReg = 1'b0;
         end
     end
     else begin 
         if (!Ss&& SSr) begin 
-            Val_o = 1'b1;
+            valReg = 1'b1;
         end
         else begin 
-            Val_o = 1'b0;
+            valReg = 1'b0;
         end
     end
 end