Добавлен модуль SpiSubSystem

sources_1/new/S5443_3Top.v

@@ -25,7 +25,7 @@ module S5443_3Top
     parameter CmdRegWidth = 32,
     parameter AddrRegWidth = 12,
     parameter STAGES = 3,
-    parameter SpiNum = 1
+    parameter SpiNum = 7
 
 )
 (
@@ -39,6 +39,7 @@ module S5443_3Top
     input SmcAre_i,
     input [1:0] SmcBe_i,
     input SmcAoe_i,
+    input [SpiNum-1:0] Ld_i,
     output [SpiNum-1:0] Ld_o,
 
     output  Led_o,
@@ -296,6 +297,7 @@ module S5443_3Top
     assign addrExt = {SmcAddr_i, 1'b0};
     assign smcValComb = (!SmcAmsN_i && !SmcAwe_i) ? 1'b1 : 1'b0;
     assign txEn = spiTxRxEn[6:0];
+     assign Mosi0_o = mosi0;
     assign Mosi1_io[0] =(SpiDir_o[0])?mosi1[0]:1'bz;
     assign Mosi1_io[1] =(SpiDir_o[1])?mosi1[1]:1'bz;
     assign Mosi1_io[2] =(SpiDir_o[2])?mosi1[2]:1'bz;
@@ -501,14 +503,6 @@ module S5443_3Top
     assign chipSelFlash[5] = spi5CsCtrlRR[1];
     assign chipSelFlash[6] = spi6CsCtrlRR[1];
     
-    assign ssMuxed[0] = (spiMode[0])? ssQ[0]:ssR[0];
-    assign ssMuxed[1] = (spiMode[1])? ssQ[1]:ssR[1];
-    assign ssMuxed[2] = (spiMode[2])? ssQ[2]:ssR[2];
-    assign ssMuxed[3] = (spiMode[3])? ssQ[3]:ssR[3];
-    assign ssMuxed[4] = (spiMode[4])? ssQ[4]:ssR[4];
-    assign ssMuxed[5] = (spiMode[5])? ssQ[5]:ssR[5];
-    assign ssMuxed[6] = (spiMode[6])? ssQ[6]:ssR[6];
-    
     assign SpiDir_o[0] = (spiMode[0])? 1'b1 : 1'b0 ;
     assign SpiDir_o[1] = (spiMode[1])? 1'b1 : 1'b0 ;
     assign SpiDir_o[2] = (spiMode[2])? 1'b1 : 1'b0 ;
@@ -517,24 +511,6 @@ module S5443_3Top
     assign SpiDir_o[5] = (spiMode[5])? 1'b1 : 1'b0 ;
     assign SpiDir_o[6] = (spiMode[6])? 1'b1 : 1'b0 ;
     
-    assign sckMuxed[0] =  (spiMode[0])?sckQ[0]:sckR[0];
-    assign sckMuxed[1] =  (spiMode[1])?sckQ[1]:sckR[1];
-    assign sckMuxed[2] =  (spiMode[2])?sckQ[2]:sckR[2];
-    assign sckMuxed[3] =  (spiMode[3])?sckQ[3]:sckR[3];
-    assign sckMuxed[4] =  (spiMode[4])?sckQ[4]:sckR[4];
-    assign sckMuxed[5] =  (spiMode[5])?sckQ[5]:sckR[5];
-    assign sckMuxed[6] =  (spiMode[6])?sckQ[6]:sckR[6];
-    
-    assign mosi0[0] =  (spiMode[0])?mosi0Q[0]:mosi0R[0];
-    assign mosi0[1] =  (spiMode[1])?mosi0Q[1]:mosi0R[1];
-    assign mosi0[2] =  (spiMode[2])?mosi0Q[2]:mosi0R[2];
-    assign mosi0[3] =  (spiMode[3])?mosi0Q[3]:mosi0R[3];
-    assign mosi0[4] =  (spiMode[4])?mosi0Q[4]:mosi0R[4];
-    assign mosi0[5] =  (spiMode[5])?mosi0Q[5]:mosi0R[5];
-    assign mosi0[6] =  (spiMode[6])?mosi0Q[6]:mosi0R[6];
-    
-    assign Mosi0_o = mosi0;
-    
     assign valToTxFifoRead[0] =  (spiMode[0])?valToTxQ[0]:valToTxR[0];
     assign valToTxFifoRead[1] =  (spiMode[1])?valToTxQ[1]:valToTxR[1];
     assign valToTxFifoRead[2] =  (spiMode[2])?valToTxQ[2]:valToTxR[2];
@@ -580,7 +556,6 @@ module S5443_3Top
     //================================================================================
     //  CODING
     //================================================================================	
-    
     DataOutMux DataOutMuxer
     (
         .Clk_i(gclk),
@@ -826,119 +801,54 @@ module S5443_3Top
     );
      
     genvar i;
-    
-    generate
-        for  (i = 0; i < SpiNum; i = i + 1) begin: SpiGen
-
-            InitRst InitRst_inst 
-            (
-                .clk_i(spiClkBus[i]),
-                .signal_o(initRstGen[i])
-            );
+    generate 
+        for (i = 0; i < SpiNum; i = i+1) begin : SpiSubSystem
+
+            SpiSubSystem #(
+                .STAGES(STAGES),
+                .CmdRegWidth(CmdRegWidth),
+                .AddrRegWidth(AddrRegWidth),
+                .WIDTH(1)
+            ) SpiSubSystem(
+                  .Clk123_i(gclk),
+                .SpiClk_i(spiClkBus[i]),
 
-            Sync1bit#(
-                .WIDTH(1),
-                .STAGES(STAGES)
-
-            )
-            Sync1bit_inst(
-                .ClkFast_i(gclk),
-                .ClkSlow_i(spiClkBus[i]),
                 .TxEn_i(txEn[i]),
-                .RstReg_i(GPIOA[i]),
-                .TxEn_o(spiTxEnSync[i]),
-                .RstReg_o(GPIOASync[i])
 
-            );
-            
-    		DataFifoWrapper #(
-                .STAGES(STAGES)
-                
-            )DataFifoWrapper
-    		(
-    			.WrClk_i(gclk),
-    			.RdClk_i(spiClkBus[i]),
-        
-    			.FifoRxRst_i(fifoRxRst[i]),
+                .FifoRxRst_i(fifoRxRst[i]),
                 .FifoTxRst_i(fifoTxRst[i]),
                 .FifoRxRstRdPtr_i(fifoRxRstRdPtr[i]),
                 .FifoTxRstWrPtr_i(fifoTxRstWrPtr[i]),
-
                 .SmcAre_i(SmcAre_i),
                 .SmcAwe_i(SmcAwe_i),
                 .SmcAddr_i(addrExt),
-    			.ToFifoVal_i(toFifoVal[i]),
-                .ToFifoRxData_i(dataToRxFifo[i]),
-                .ToFifoRxWriteVal_i(valToRxFifo[i]),
-                .ToFifoTxReadVal_i(valToTxFifoRead[i]),
-    			.ToFifoData_i(toFifoData[32*i+:32]),
-
-    			.TxFifoCtrlReg_o(txFifoCtrlReg[i]),
-                .RxFifoCtrlReg_o(rxFifoCtrlReg[i]),
-                .EmptyFlagTx_o(emptyFlagTx[i]),
-                .DataFromRxFifo_o(dataFromRxFifo[i]),
-    			.ToSpiData_o(toSpiData[i])
-    		);
-    
-            SPIm SPIm_inst (
-                .Clk_i(spiClkBus[i]),
-                .Start_i(spiTxEnSync[i]),
-                .Rst_i(initRstGen[i]| spiMode[i] | !spiEn[i]),
-                .EmptyFlag_i(emptyFlagTx[i]),
-                .SpiData_i(toSpiData[i]),
-                .Sck_o(sckR[i]),
-                .Ss_o(ssR[i]),
-                .Mosi0_o(mosi0R[i]),
+                .ToFifoVal_i(toFifoVal[i]),
+                .ToFifoData_i(toFifoData[32*i+:32]),
                 .WidthSel_i(widthSel[i]),
                 .PulsePol_i(clockPol[i]),
                 .ClockPhase_i(clockPhase[i]),
                 .EndianSel_i(endianSel[i]),
                 .Lag_i(lag[i]),
                 .Lead_i(leadx[i]),
-                .Stop_i(stopDelay[i]),
-                .SelSt_i(selSt[i]),
-                .Val_o(valToTxR[i])
-    
-            );
-    
-            SPIs SPIs_inst (
-                .Clk_i(spiClkBus[i]),
-                .Rst_i(initRstGen[i] | spiMode[i]),
-                .Sck_i(sckR[i]),
-                .Ss_i(ssR[i]),
-                .Mosi0_i(Mosi1_io[i]),
-                .WidthSel_i(widthSel[i]),
-                .EndianSel_i(endianSel[i]),
                 .SelSt_i(selSt[i]),
-                .DataToRxFifo_o(dataToRxFifoR[i]),
-                .Val_o(valToRxR[i])
-            );
-    
-            QuadSPIm QuadSPIm_inst (
-                .Clk_i(spiClkBus[i]),
-                .Start_i(spiTxEnSync[i]),
-                .Rst_i(initRstGen[i]| !spiMode[i] | !spiEn[i]),
-                .EmptyFlag_i(emptyFlagTx[i]),
-                .SpiData_i(toSpiData[i]),
-                .Sck_o(sckQ[i]),
-                .Ss_o(ssQ[i]),
-                .Mosi0_o(mosi0Q[i]),
+                .Stop_i(stopDelay[i]),
+                .SpiMode_i(spiMode[i]),
+                .SpiEn_i(spiEn[i]),
+                
+                .TxFifoCtrlReg_o(txFifoCtrlReg[i]),
+                .RxFifoCtrlReg_o(rxFifoCtrlReg[i]),
+                .DataFromRxFifo_o(dataFromRxFifo[i]),
+
+                .Sck_o(sckMuxed[i]),
+                .Ss_o(ssMuxed[i]),
+                .Mosi0_o(mosi0[i]),
                 .Mosi1_o(mosi1[i]),
                 .Mosi2_o(mosi2[i]),
-                .Mosi3_o(mosi3[i]),
-                .WidthSel_i(widthSel[i]),
-                .PulsePol_i(clockPol[i]),
-                .ClockPhase_i(clockPhase[i]),
-                .EndianSel_i(endianSel[i]),
-                .Lag_i(lag[i]),
-                .Lead_i(leadx[i]),
-                .Stop_i(stopDelay[i]),
-                .SelSt_i(selSt[i]),
-                .Val_o(valToTxQ[i])
+                .Mosi3_o(mosi3[i])
             );
         end
     endgenerate
-    
+
     InitRst InitRst_inst
      (
         .clk_i(gclk),

sources_1/new/SpiSubSystem/SpiLinesMuxer.v

@@ -0,0 +1,43 @@
+module SpiLinesMuxer (
+    input SsR_i,
+    input SsQ_i,
+    input SckR_i,
+    input SckQ_i,
+    input Mosi0R_i,
+    input Mosi0Q_i,
+
+    input ChipSelFpga_i,
+    input ChipSelFlash_i,
+    input Assel_i,
+    input SpiMode_i,
+
+    output Ss_o,
+    output SsFlash_o,
+    output Sck_o,
+    output Mosi0_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+wire ssMuxed;
+wire sckMuxed;
+wire mosi0Muxed;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign sckMuxed = (SpiMode_i) ? SckQ_i : SckR_i;
+assign ssMuxed = (SpiMode_i) ? SsQ_i : SsR_i;
+assign mosi0Muxed = (SpiMode_i) ? Mosi0Q_i : Mosi0R_i;
+
+assign Ss_o = (Assel_i) ? (ChipSelFpga_i ? ssMuxed : 1'b1) : ChipSelFpga_i;
+assign SsFlash_o = (Assel_i) ? (ChipSelFlash_i ? ssMuxed:1'b1) : ChipSelFlash_i;
+//================================================================================
+//	CODING
+//================================================================================
+
+
+
+
+
+endmodule

sources_1/new/SpiSubSystem/SpiSubSystem.v

@@ -0,0 +1,179 @@
+module SpiSubSystem #(
+    parameter STAGES = 3,
+    parameter CmdRegWidth = 32,
+    parameter AddrRegWidth = 12,
+    parameter WIDTH  = 1 
+) (
+    input Clk123_i,
+    input SpiClk_i,
+
+    input TxEn_i,
+
+    input FifoRxRst_i,
+    input FifoTxRst_i,
+    input FifoRxRstRdPtr_i,
+    input FifoTxRstWrPtr_i,
+    input SmcAre_i,
+    input SmcAwe_i,
+    input [AddrRegWidth-1:0] SmcAddr_i,
+    input ToFifoVal_i,
+    input [CmdRegWidth-1:0] ToFifoData_i,
+
+    input [1:0] WidthSel_i,
+    input PulsePol_i,
+    input ClockPhase_i,
+    input EndianSel_i,
+    input Lag_i,
+    input Lead_i,
+    input SelSt_i,
+    input [5:0] Stop_i,
+
+    input SpiMode_i,
+    input SpiEn_i,
+
+    output [CmdRegWidth-1:0] TxFifoCtrlReg_o,
+    output [CmdRegWidth-1:0] RxFifoCtrlReg_o,
+    output [CmdRegWidth-1:0] DataFromRxFifo_o,
+
+    output Sck_o,
+    output Ss_o,
+    output Mosi0_o,
+    output Mosi1_o,
+    output Mosi2_o,
+    output Mosi3_o
+);
+//================================================================================
+//	REG/WIRE
+//================================================================================
+wire [CmdRegWidth-1:0] toSpiData;
+wire emptyFlagTx;
+wire initRst;
+
+wire sckR;
+wire ssR;
+wire mosi0R;
+wire valToTxR;
+wire valToRxR;
+
+wire sckQ;
+wire ssQ;
+wire mosi0Q;
+wire valToTxQ;
+
+wire valToTxFifoRead;
+wire valToRxFifoWrite;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign  Sck_o   =   (SpiMode_i) ? sckQ : sckR;
+assign  Mosi0_o =   (SpiMode_i) ? mosi0Q : mosi0R;
+assign  Ss_o    =   (SpiMode_i) ? ssQ : ssR;
+
+assign valToTxFifoRead  = (SpiMode_i) ? valToTxQ : valToTxR;
+
+//================================================================================
+//	CODING
+//================================================================================
+InitRst InitRst_inst
+(
+    .clk_i(SpiClk_i),
+    .signal_o(initRst)
+
+);
+
+Sync1bit #(
+    .WIDTH(1),
+    .STAGES(STAGES)
+) Sync1bit_inst (
+    .ClkFast_i(Clk123_i),
+    .ClkSlow_i(SpiClk_i),
+    .TxEn_i(TxEn_i),
+    .TxEn_o(spiTxEnSync)
+);
+
+DataFifoWrapper #(
+    .STAGES(STAGES)
+) DataFifoWrapper
+(
+    .WrClk_i(Clk123_i),
+    .RdClk_i(SpiClk_i),
+
+    .FifoRxRst_i(FifoRxRst_i),
+    .FifoTxRst_i(FifoTxRst_i),
+    .FifoRxRstRdPtr_i(FifoRxRstRdPtr_i),
+    .FifoTxRstWrPtr_i(FifoTxRstWrPtr_i),
+
+    .SmcAre_i(SmcAre_i),
+    .SmcAwe_i(SmcAwe_i),
+    .SmcAddr_i(SmcAddr_i),
+    .ToFifoVal_i(ToFifoVal_i),
+    .ToFifoRxData_i(dataToRxFifo),
+    .ToFifoRxWriteVal_i(valToRxR),
+    .ToFifoTxReadVal_i(valToTxFifoRead),
+    .ToFifoData_i(ToFifoData_i),
+
+    .TxFifoCtrlReg_o(TxFifoCtrlReg_o),
+    .RxFifoCtrlReg_o(RxFifoCtrlReg_o),
+    .EmptyFlagTx_o(emptyFlagTx),
+    .DataFromRxFifo_o(DataFromRxFifo_o),
+    .ToSpiData_o(toSpiData)
+);
+
+SPIm SPIm_inst (
+    .Clk_i(SpiClk_i),
+    .Start_i(spiTxEnSync),
+    .Rst_i(initRst | SpiMode_i | !SpiEn_i),
+    .EmptyFlag_i(emptyFlagTx),
+    .SpiData_i(toSpiData),
+    .WidthSel_i(WidthSel_i),
+    .PulsePol_i(PulsePol_i),
+    .ClockPhase_i(ClockPhase_i),
+    .EndianSel_i(EndianSel_i),
+    .Lag_i(Lag_i),
+    .Lead_i(Lead_i),
+    .Stop_i(Stop_i),
+    .SelSt_i(SelSt_i),
+    .Sck_o(sckR),
+    .Ss_o(ssR),
+    .Mosi0_o(mosi0R),
+    .Val_o(valToTxR)
+);
+
+SPIs SPIs_inst (
+    .Clk_i(SpiClk_i),
+    .Rst_i(initRst | SpiMode_i),
+    .Sck_i(sckR),
+    .Ss_i(ssR),
+    .Mosi0_i(Mosi1_io),
+    .WidthSel_i(WidthSel_i),
+    .EndianSel_i(EndianSel_i),
+    .SelSt_i(SelSt_i),
+    .DataToRxFifo_o(dataToRxFifo),
+    .Val_o(valToRxR)
+);
+
+QuadSPIm QuadSPIm_inst (
+    .Clk_i(SpiClk_i),
+    .Start_i(spiTxEnSync),
+    .Rst_i(initRst | !SpiMode_i | !SpiEn_i),
+    .EmptyFlag_i(emptyFlagTx),
+    .SpiData_i(toSpiData),
+    .WidthSel_i(WidthSel_i),
+    .PulsePol_i(PulsePol_i),
+    .ClockPhase_i(ClockPhase_i),
+    .EndianSel_i(EndianSel_i),
+    .Lag_i(Lag_i),
+    .Lead_i(Lead_i),
+    .Stop_i(Stop_i),
+    .SelSt_i(SelSt_i),
+    .Sck_o(sckQ),
+    .Ss_o(ssQ),
+    .Mosi0_o(mosi0_q),
+    .Mosi1_o(Mosi1_o),
+    .Mosi2_o(Mosi2_o),
+    .Mosi3_o(Mosi3_o),
+    .Val_o(valToTxQ)
+);
+
+endmodule