RegMap and Top changes

SRAM/QuadSPIm.v

@@ -1,3 +1,4 @@
+
 module QuadSPIm(
     input Clk_i,
     input Rst_i,

constrs_1/new/S5443_3.xdc

@@ -89,13 +89,13 @@ set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}]
 set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}]
-set_property PACKAGE_PIN J3 [get_ports {Mosi1_i[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[0]}]
+set_property PACKAGE_PIN J3 [get_ports {Mosi1_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[0]}]
 set_property PACKAGE_PIN H2 [get_ports {Mosi2_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}]
 set_property PACKAGE_PIN L1  [get_ports {Mosi3_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}]
-set_property PACKAGE_PIN J2 [get_ports {SpiRs_i[0]}]
+set_property PACKAGE_PIN J2 [get_ports {SpiRst_i[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_i[0]}]
 
 #SPI1
@@ -105,8 +105,8 @@ set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}]
 set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}]
-set_property PACKAGE_PIN R2 [get_ports {Mosi1_i[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[1]}]
+set_property PACKAGE_PIN R2 [get_ports {Mosi1_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[1]}]
 set_property PACKAGE_PIN N1 [get_ports {Mosi2_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[1]}]
 set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}]
@@ -122,8 +122,8 @@ set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}]
 set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}]
-set_property PACKAGE_PIN D2 [get_ports {Mosi1_i[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[2]}]
+set_property PACKAGE_PIN D2 [get_ports {Mosi1_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[2]}]
 set_property PACKAGE_PIN F2 [get_ports {Mosi2_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[2]}]
 set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}]
@@ -138,8 +138,8 @@ set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}]
 set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}]
-set_property PACKAGE_PIN R8 [get_ports {Mosi1_i[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[3]}]
+set_property PACKAGE_PIN R8 [get_ports {Mosi1_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[3]}]
 set_property PACKAGE_PIN R11 [get_ports {Mosi2_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[3]}]
 set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}]
@@ -156,8 +156,8 @@ set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}]
 set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}]
-set_property PACKAGE_PIN P12 [get_ports {Mosi1_i[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {Mosi_o[4]}]
+set_property PACKAGE_PIN P12 [get_ports {Mosi1_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[4]}]
 set_property PACKAGE_PIN M15 [get_ports {Mosi2_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[4]}]
 set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}]
@@ -173,8 +173,8 @@ set_property PACKAGE_PIN R5 [get_ports {Ss_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}]
 set_property PACKAGE_PIN R4 [get_ports {Mosi0_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}]
-set_property PACKAGE_PIN R3 [get_ports {Mosi1_i[5]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[5]}]
+set_property PACKAGE_PIN R3 [get_ports {Mosi1_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[5]}]
 set_property PACKAGE_PIN N7 [get_ports {Mosi2_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[5]}]
 set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}]
@@ -190,8 +190,8 @@ set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}]
 set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}]
-set_property PACKAGE_PIN C4 [get_ports {Mosi1_i[6]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {Miso1_o[6]}]
+set_property PACKAGE_PIN C4 [get_ports {Mosi1_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[6]}]
 set_property PACKAGE_PIN B4 [get_ports {Mosi2_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[6]}]
 set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[6]}]

sources_1/new/S5443_3Top.v

@@ -1,3 +1,4 @@
+
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 // Company: 
@@ -62,23 +63,100 @@ wire clk80;
 wire clk61;
 wire Rst_i;
 wire gclk;
-wire [15:0] baudRate;
+wire [15:0] baudRate [SpiNum-1:0];
 wire [19:0] baudRateexp;
 
+//SPI0
+wire [CmdRegWidth-1:0] Spi0Ctrl;
+wire [CmdRegWidth-1:0] Spi0Clk;
+wire [CmdRegWidth-1:0] Spi0CsDelay;
+wire [CmdRegWidth-1:0] Spi0CsCtrl;
+wire [CmdRegWidth-1:0] Spi0TxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi0RxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi0TxFifo;
+wire [CmdRegWidth-1:0] Spi0RxFifo;
+//SPI1
+wire [CmdRegWidth-1:0] Spi1Ctrl;
+wire [CmdRegWidth-1:0] Spi1Clk;
+wire [CmdRegWidth-1:0] Spi1CsDelay;
+wire [CmdRegWidth-1:0] Spi1CsCtrl;
+wire [CmdRegWidth-1:0] Spi1TxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi1RxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi1TxFifo;
+wire [CmdRegWidth-1:0] Spi1RxFifo;
+//SPI2
+wire [CmdRegWidth-1:0] Spi2Ctrl;
+wire [CmdRegWidth-1:0] Spi2Clk;
+wire [CmdRegWidth-1:0] Spi2CsDelay;
+wire [CmdRegWidth-1:0] Spi2CsCtrl;
+wire [CmdRegWidth-1:0] Spi2TxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi2RxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi2TxFifo;
+wire [CmdRegWidth-1:0] Spi2RxFifo;
+//SPI3
+wire [CmdRegWidth-1:0] Spi3Ctrl;
+wire [CmdRegWidth-1:0] Spi3Clk;
+wire [CmdRegWidth-1:0] Spi3CsDelay;
+wire [CmdRegWidth-1:0] Spi3CsCtrl;
+wire [CmdRegWidth-1:0] Spi3TxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi3RxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi3TxFifo;
+wire [CmdRegWidth-1:0] Spi3RxFifo;
+//SPI4
+wire [CmdRegWidth-1:0] Spi4Ctrl;
+wire [CmdRegWidth-1:0] Spi4Clk;
+wire [CmdRegWidth-1:0] Spi4CsDelay;
+wire [CmdRegWidth-1:0] Spi4CsCtrl;
+wire [CmdRegWidth-1:0] Spi4TxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi4RxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi4TxFifo;
+wire [CmdRegWidth-1:0] Spi4RxFifo;
+//SPI5
+wire [CmdRegWidth-1:0] Spi5Ctrl;
+wire [CmdRegWidth-1:0] Spi5Clk;
+wire [CmdRegWidth-1:0] Spi5CsDelay;
+wire [CmdRegWidth-1:0] Spi5CsCtrl;
+wire [CmdRegWidth-1:0] Spi5TxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi5RxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi5TxFifo;
+wire [CmdRegWidth-1:0] Spi5RxFifo;
+//SPI6
+wire [CmdRegWidth-1:0] Spi6Ctrl;
+wire [CmdRegWidth-1:0] Spi6Clk;
+wire [CmdRegWidth-1:0] Spi6CsDelay;
+wire [CmdRegWidth-1:0] Spi6CsCtrl;
+wire [CmdRegWidth-1:0] Spi6TxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi6RxFifoCtrl;
+wire [CmdRegWidth-1:0] Spi6TxFifo;
+wire [CmdRegWidth-1:0] Spi6RxFifo;
+
+wire [CmdRegWidth-1:0] SpiTxRxEn;
+wire [CmdRegWidth-1:0] GPIOA;
+
+
+
+
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
 assign addr = {Addr_i, 1'b0};
 assign Data_i = (!outputEn_i) ? data : 16'bz;
-assign ten = 8'b00000001;
+assign ten = SpiTxRxEn[6:0];
 assign Mosi0_o = Mosi0;
 assign Mosi1_o = Mosi1;
 assign Mosi2_o = Mosi2;
 assign Mosi3_o = Mosi3;
 assign Ss_o = Ss;
 assign Sck_o = Sck;
-assign baudRate = 16'h4;
-assign baudRateexp = baudRate*13+1;
+// assign baudRate[15:0][0] =Spi0Clk[15:0];
+// assign baudRate[15:0][1] =Spi1Clk[15:0];
+// assign baudRate[15:0][2] =Spi2Clk[15:0];
+// assign baudRate[15:0][3] =Spi3Clk[15:0];
+// assign baudRate[15:0][4] =Spi4Clk[15:0];
+// assign baudRate[15:0][5] =Spi5Clk[15:0];
+// assign baudRate[15:0][6] =Spi6Clk[15:0];
+
+
 //================================================================================
 //  CODING
 //================================================================================	
@@ -131,7 +209,73 @@ RegMap_inst (
     .rdEn_i(readEn_i),
     .BE_i(BE_i),
     .Led_o(Led_o),
-    .AnsDataReg_o(data)
+    .AnsDataReg_o(data),
+    //Spi0
+    .Spi0CtrlReg_o(Spi0Ctrl),
+    .Spi0ClkReg_o(Spi0Clk),
+    .Spi0CsDelayReg_o(Spi0CsDelay),
+    .Spi0CsCtrlReg_o(Spi0CsCtrl),
+    .Spi0TxFifoCtrlReg_o(Spi0TxFifoCtrl),
+    .Spi0RxFifoCtrlReg_o(Spi0RxFifoCtrl),
+    .Spi0TxFifoReg_o(Spi0TxFifo),
+    .Spi0RxFifoReg_o(Spi0RxFifo),
+    //Spi1
+    .Spi1CtrlReg_o(Spi1Ctrl),
+    .Spi1ClkReg_o(Spi1Clk),
+    .Spi1CsDelayReg_o(Spi1CsDelay),
+    .Spi1CsCtrlReg_o(Spi1CsCtrl),
+    .Spi1TxFifoCtrlReg_o(Spi1TxFifoCtrl),
+    .Spi1RxFifoCtrlReg_o(Spi1RxFifoCtrl),
+    .Spi1TxFifoReg_o(Spi1TxFifo),
+    .Spi1RxFifoReg_o(Spi1RxFifo),
+    //Spi2
+    .Spi2CtrlReg_o(Spi2Ctrl),
+    .Spi2ClkReg_o(Spi2Clk),
+    .Spi2CsDelayReg_o(Spi2CsDelay),
+    .Spi2CsCtrlReg_o(Spi2CsCtrl),
+    .Spi2TxFifoCtrlReg_o(Spi2TxFifoCtrl),
+    .Spi2RxFifoCtrlReg_o(Spi2RxFifoCtrl),
+    .Spi2TxFifoReg_o(Spi2TxFifo),
+    .Spi2RxFifoReg_o(Spi2RxFifo),
+    //Spi3
+    .Spi3CtrlReg_o(Spi3Ctrl),
+    .Spi3ClkReg_o(Spi3Clk),
+    .Spi3CsDelayReg_o(Spi3CsDelay),
+    .Spi3CsCtrlReg_o(Spi3CsCtrl),
+    .Spi3TxFifoCtrlReg_o(Spi3TxFifoCtrl),
+    .Spi3RxFifoCtrlReg_o(Spi3RxFifoCtrl),
+    .Spi3TxFifoReg_o(Spi3TxFifo),
+    .Spi3RxFifoReg_o(Spi3RxFifo),
+    //Spi4
+    .Spi4CtrlReg_o(Spi4Ctrl),
+    .Spi4ClkReg_o(Spi4Clk),
+    .Spi4CsDelayReg_o(Spi4CsDelay),
+    .Spi4CsCtrlReg_o(Spi4CsCtrl),
+    .Spi4TxFifoCtrlReg_o(Spi4TxFifoCtrl),
+    .Spi4RxFifoCtrlReg_o(Spi4RxFifoCtrl),
+    .Spi4TxFifoReg_o(Spi4TxFifo),
+    .Spi4RxFifoReg_o(Spi4RxFifo),
+    //Spi5
+    .Spi5CtrlReg_o(Spi5Ctrl),
+    .Spi5ClkReg_o(Spi5Clk),
+    .Spi5CsDelayReg_o(Spi5CsDelay),
+    .Spi5CsCtrlReg_o(Spi5CsCtrl),
+    .Spi5TxFifoCtrlReg_o(Spi5TxFifoCtrl),
+    .Spi5RxFifoCtrlReg_o(Spi5RxFifoCtrl),
+    .Spi5TxFifoReg_o(Spi5TxFifo),
+    .Spi5RxFifoReg_o(Spi5RxFifo),
+    //Spi6
+    .Spi6CtrlReg_o(Spi6Ctrl),
+    .Spi6ClkReg_o(Spi6Clk),
+    .Spi6CsDelayReg_o(Spi6CsDelay),
+    .Spi6CsCtrlReg_o(Spi6CsCtrl),
+    .Spi6TxFifoCtrlReg_o(Spi6TxFifoCtrl),
+    .Spi6RxFifoCtrlReg_o(Spi6RxFifoCtrl),
+    .Spi6TxFifoReg_o(Spi6TxFifo),
+    .Spi6RxFifoReg_o(Spi6RxFifo),
+
+    .SpiTxRxEnReg_o(SpiTxRxEn),
+    .GPIOAReg_o(GPIOA)
 
 );