Merge branch 'master' of \\192.168.211.254\Public\S5443\FPGA\S5443v3_REPO

# Conflicts:
#	sources_1/new/Mux/DataMuxer.v
#	sources_1/new/S5443_3Top.v

SRAM/QuadSPIm.v

@@ -20,7 +20,7 @@ module QuadSPIm(
     output reg Mosi2_i,
     output reg Mosi3_i,
     output reg  Sck_o,
-    output reg Val_o,
+    output  Val_o,
     output Ss_o
 
 );
@@ -28,6 +28,10 @@ module QuadSPIm(
 //  REG/WIRE
 //================================================================================
 reg startFlag;
+reg startR;
+reg [31:0] trCnt;
+reg valReg;
+reg valToRxFifo1;
 reg [2:0] ssCnt;
 reg Ss;
 reg SSr;
@@ -46,11 +50,41 @@ wire SsPol = SELST_i ? Ss : ~Ss;
 //================================================================================
 
 assign Ss_o = SsPol; 
-
+assign Val_o = (trCnt < 1 ) ?valToRxFifo1:valReg;
 //================================================================================
 //  CODING
 //================================================================================	
 
+always @(posedge Clk_i) begin 
+    startR <= Start_i;
+end
+
+always @(*) begin 
+    if (Rst_i) begin 
+        valToRxFifo1 = 1'b0;
+    end
+    else begin 
+        if (Start_i && !startR) begin 
+            valToRxFifo1 = 1'b1;
+        end
+        else begin 
+            valToRxFifo1 = 1'b0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        trCnt <= 1'b0;
+    end
+    else begin 
+        if ( (ssNum + LEAD_i + LAG_i)-1) begin 
+            trCnt <= trCnt + 1'b1;
+        end
+    end
+end
+
+
 
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
@@ -240,18 +274,18 @@ end
 always @(*) begin
     if (SELST_i) begin 
         if (Ss && !SSr) begin 
-            Val_o = 1'b1;
+            valReg = 1'b1;
         end
         else begin 
-            Val_o = 1'b0;
+            valReg = 1'b0;
         end
     end
     else begin 
         if (!Ss&& SSr) begin 
-            Val_o = 1'b1;
+            valReg = 1'b1;
         end
         else begin 
-            Val_o = 1'b0;
+            valReg = 1'b0;
         end
     end
 end

SRAM/QuadSPIs.v

@@ -9,8 +9,13 @@ module QuadSPIs (
     input Mosi2_i,
     input Mosi3_i,
 
+    input [1:0] WidthSel_i,
+    input SELST_i,
+   
+
     output reg [23:0] Data_o,
     output reg [7:0] Addr_o,
+      output [31:0] DataToRxFifo_o,
     output reg Val_o
 );
 
@@ -19,34 +24,88 @@ module QuadSPIs (
 //================================================================================
 
 reg ssReg;
-reg ssRegR;
-reg RorWFlag;
-
-reg [3:0] cnt; 
+reg ssRegR; 
+reg SckReg; 
 reg [7:0] addrReg;
-reg [7:0] shiftReg0R;
-reg [7:0] shiftReg1R;
-reg [7:0] shiftReg2R;
-reg [7:0] shiftReg0RR;
-reg [7:0] shiftReg1RR;
-reg [7:0] shiftReg2RR;
 reg [7:0] shiftReg0;
 reg [7:0] shiftReg1;
 reg [7:0] shiftReg2;
+
+reg [7:0] shiftReg0M;
+reg [7:0] shiftReg1M;
+reg [7:0] shiftReg2M;
+reg [7:0] addrRegM;
+
+
+//===============================================================================
+//  ASSIGNMENTS
+
+
+assign DataToRxFifo_o = {Addr_o, Data_o};
+
 //================================================================================
 //	CODING
 //================================================================================
 
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin
+        addrRegM = 8'h0; 
+        shiftReg0M = 8'h0;
+        shiftReg1M = 8'h0;
+        shiftReg2M = 8'h0;
+    end
+    else begin 
+        case(WidthSel_i)  
+             0: begin 
+                addrRegM   = addrReg  [1:0];
+                shiftReg0M = shiftReg0[1:0];
+                shiftReg1M = shiftReg1[1:0];
+                shiftReg2M = shiftReg2[1:0];
+            end
+            1: begin 
+                addrRegM   = addrReg  [3:0];
+                shiftReg0M = shiftReg0[3:0];
+                shiftReg1M = shiftReg1[3:0];
+                shiftReg2M = shiftReg2[3:0];
+            end
+            2: begin 
+                addrRegM   = addrReg  [5:0];
+                shiftReg0M = shiftReg0[5:0];
+                shiftReg1M = shiftReg1[5:0];
+                shiftReg2M = shiftReg2[5:0];
+            end
+            3: begin 
+                addrRegM   = addrReg  [7:0];
+                shiftReg0M = shiftReg0[7:0];
+                shiftReg1M = shiftReg1[7:0];
+                shiftReg2M = shiftReg2[7:0];
+            end
+        endcase
+    end
+end
+
+
+
 always @(posedge Clk_i) begin 
     if (Rst_i) begin 
         Data_o <= 24'h0;
     end
-    else begin 
-        if (ssReg && !ssRegR) begin 
-            Data_o <= {shiftReg2, shiftReg1, shiftReg0};
+    else begin
+        if (SELST_i) begin  
+            if (ssReg && !ssRegR) begin 
+                Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
+            end
         end
         else begin 
-            Data_o <= 24'h0;
+            if (!ssReg && ssRegR) begin 
+                Data_o <= {shiftReg2M, shiftReg1M, shiftReg0M};
+            end
         end
     end
 end
@@ -55,24 +114,43 @@ always @(posedge Clk_i) begin
     if (Rst_i) begin 
         Addr_o <= 8'h0;
     end
-    else begin 
-        if (ssReg && !ssRegR) begin 
-            Addr_o <= addrReg;
+    else begin
+        if (SELST_i) begin 
+            if (ssReg && !ssRegR) begin 
+                Addr_o <= addrRegM;
+            end
+        end
+        else begin 
+            if (!ssReg && ssRegR) begin 
+                Addr_o <= addrRegM;
+            end
         end
     end
 end
 
 
+
+
 always @(posedge Sck_i) begin 
     if (Rst_i) begin 
         shiftReg0 <= 8'h0;
     end
-    else begin 
-        if (!Ss_i) begin 
-            shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
+            end
+            else begin 
+                shiftReg0 <= 8'h0;
+            end
         end
         else begin 
-            shiftReg0 <= 8'h0;
+            if (Ss_i) begin 
+                shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
+            end
+            else begin 
+                shiftReg0<= 8'h0;
+            end
         end
     end
 end
@@ -82,12 +160,22 @@ always @(posedge Sck_i ) begin
     if (Rst_i) begin 
         shiftReg1 <= 8'h0;
     end
-    else begin 
-        if (!Ss_i) begin 
-            shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
+            end
+            else begin 
+                shiftReg1 <= 8'h0;
+            end
         end
         else begin 
-            shiftReg1 <= 8'h0;
+            if (Ss_i) begin 
+                shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
+            end
+            else begin 
+                shiftReg1 <= 8'h0;
+            end
         end
     end
 end
@@ -97,12 +185,22 @@ always @(posedge Sck_i ) begin
     if (Rst_i) begin 
         shiftReg2 <= 8'h0;
     end
-    else begin 
-        if (!Ss_i) begin 
-            shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
+            end
+            else begin 
+                shiftReg2 <= 8'h0;
+            end
         end
         else begin 
-            shiftReg2 <= 8'h0;
+            if (Ss_i) begin 
+                shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
+            end
+            else begin 
+                shiftReg2 <= 8'h0;
+            end
         end
     end
 end
@@ -112,35 +210,44 @@ always @(posedge Sck_i ) begin
     if (Rst_i) begin 
         addrReg <= 8'h0;
     end
-    else begin 
-        if (!Ss_i) begin 
-            addrReg <= {addrReg[6:0], Mosi3_i};
+    else begin
+        if (SELST_i) begin 
+            if (!Ss_i) begin 
+                addrReg <= {addrReg[6:0], Mosi3_i};
+            end
+            else begin 
+                addrReg <= 8'h0;
+            end
         end
         else begin 
-            addrReg <= 8'h0;
+            if (Ss_i) begin 
+                addrReg <= {addrReg[6:0], Mosi3_i};
+            end
+            else begin 
+                addrReg <= 8'h0;
+            end
         end
     end
 end
 
 
-always	@(posedge	Clk_i)	begin
-	ssReg	<=	Ss_i;
-	ssRegR	<=	ssReg;
-    shiftReg0R <= shiftReg0;
-    shiftReg1R <= shiftReg1;
-    shiftReg2R <= shiftReg2;
-    shiftReg0RR <= shiftReg0R;
-    shiftReg1RR <= shiftReg1R;
-    shiftReg2RR <= shiftReg2R;
-end
-
 
-always @(posedge Clk_i) begin 
-    if (ssReg && !ssRegR) begin 
-        Val_o <= 1'b1;
+always @(posedge Clk_i) begin
+    if (SELST_i) begin 
+        if (ssReg && !ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
     end
     else begin 
-        Val_o <= 1'b0;
+        if (!ssReg&& ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
     end
 end
 

constrs_1/new/S5443_3.xdc

@@ -95,12 +95,12 @@ set_property PACKAGE_PIN J3 [get_ports {Mosi1_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[0]}]
 set_property PACKAGE_PIN H2 [get_ports {Mosi2_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}]
-set_property PACKAGE_PIN L1  [get_ports {Mosi3_o[0]}]
+set_property PACKAGE_PIN L1 [get_ports {Mosi3_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}]
 set_property PACKAGE_PIN J2 [get_ports {SpiRst_o[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[0]}]
-set_property PACKAGE_PIN M13 [get_ports {LD_i[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[0]}]
+set_property PACKAGE_PIN M13 [get_ports {Ld_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[0]}]
 
 
 
@@ -121,8 +121,8 @@ set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[1]}]
 set_property PACKAGE_PIN P2 [get_ports {SpiRst_o[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[1]}]
-set_property PACKAGE_PIN N11 [get_ports {LD_i[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[1]}]
+set_property PACKAGE_PIN N11 [get_ports {Ld_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[1]}]
 
 
 
@@ -143,8 +143,8 @@ set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[2]}]
 set_property PACKAGE_PIN E3 [get_ports {SpiRst_o[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[2]}]
-set_property PACKAGE_PIN N9 [get_ports {LD_i[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[2]}]
+set_property PACKAGE_PIN N9 [get_ports {Ld_i[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[2]}]
 
 
 #SPI3
@@ -164,8 +164,8 @@ set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[3]}]
 set_property PACKAGE_PIN R9 [get_ports {SpiRst_o[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[3]}]
-set_property PACKAGE_PIN N13 [get_ports {LD_i[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[3]}]
+set_property PACKAGE_PIN N13 [get_ports {Ld_i[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[3]}]
 
 
 
@@ -187,8 +187,8 @@ set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[4]}]
 set_property PACKAGE_PIN N15 [get_ports {SpiRst_o[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[4]}]
-set_property PACKAGE_PIN P15 [get_ports {LD_i[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[4]}]
+set_property PACKAGE_PIN P15 [get_ports {Ld_i[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[4]}]
 
 
 
@@ -209,8 +209,8 @@ set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]
 set_property PACKAGE_PIN N6 [get_ports {SpiRst_o[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[5]}]
-set_property PACKAGE_PIN N12 [get_ports {LD_i[5]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[5]}]
+set_property PACKAGE_PIN N12 [get_ports {Ld_i[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[5]}]
 
 
 #SPI6
@@ -230,8 +230,8 @@ set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[6]}]
 set_property PACKAGE_PIN A2 [get_ports {SpiRst_o[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[6]}]
-set_property PACKAGE_PIN M8 [get_ports {LD_i[6]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {LD_i[6]}]
+set_property PACKAGE_PIN M8 [get_ports {Ld_i[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[6]}]
 
 
 set_property PACKAGE_PIN M7 [get_ports LD_o]
@@ -268,3 +268,38 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
 
 
 
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list gclk]]
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
+set_property port_width 7 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {Ss_o_OBUF[0]} {Ss_o_OBUF[1]} {Ss_o_OBUF[2]} {Ss_o_OBUF[3]} {Ss_o_OBUF[4]} {Ss_o_OBUF[5]} {Ss_o_OBUF[6]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
+set_property port_width 16 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {SmcData_i_IBUF[0]} {SmcData_i_IBUF[1]} {SmcData_i_IBUF[2]} {SmcData_i_IBUF[3]} {SmcData_i_IBUF[4]} {SmcData_i_IBUF[5]} {SmcData_i_IBUF[6]} {SmcData_i_IBUF[7]} {SmcData_i_IBUF[8]} {SmcData_i_IBUF[9]} {SmcData_i_IBUF[10]} {SmcData_i_IBUF[11]} {SmcData_i_IBUF[12]} {SmcData_i_IBUF[13]} {SmcData_i_IBUF[14]} {SmcData_i_IBUF[15]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
+set_property port_width 11 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {SmcAddr_i_IBUF[0]} {SmcAddr_i_IBUF[1]} {SmcAddr_i_IBUF[2]} {SmcAddr_i_IBUF[3]} {SmcAddr_i_IBUF[4]} {SmcAddr_i_IBUF[5]} {SmcAddr_i_IBUF[6]} {SmcAddr_i_IBUF[7]} {SmcAddr_i_IBUF[8]} {SmcAddr_i_IBUF[9]} {SmcAddr_i_IBUF[10]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 1 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list SmcAre_i_IBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list SmcAwe_i_IBUF]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets gclk]

sources_1/new/DataFifo/DataFifoWrapper.v

@@ -11,17 +11,32 @@ module DataFifoWrapper
 	input	RdClk_i,
     input	Rst_i,
 	input   SmcAre_i,
+	input	SmcAwe_i,
 
 	input	ToFifoVal_i,
 	input	[CmdRegWidth-1:0]	ToFifoData_i,
+	input   [CmdRegWidth-1:0]	ToFifoRxData_i,
+	input   ToFifoRxWriteVal_i,                   
 	
+	input ToFifoTxReadVal_i,
+
 	output	ToSpiVal_o,
-	output	[CmdRegWidth-1:0]	ToSpiData_o
+	output	[CmdRegWidth-1:0]	ToSpiData_o,
+	output  [CmdRegWidth-1:0]   DataFromRxFifo_o
 );
 //================================================================================
 //	REG/WIRE
 //================================================================================
-	
+	wire [CmdRegWidth-1:0]	dataFromRxFifo;
+	wire fullFlagRx;
+	wire emptyFlagRx;
+	wire fullFlagTx;
+	wire emptyFlagTx;
+
+	wire txFifoWrEn;
+	wire txFifoRdEn;
+	wire rxFifoWrEn;
+	wire rxFifoRdEn;
 //================================================================================
 //	ASSIGNMENTS
 //================================================================================
@@ -34,16 +49,50 @@ module DataFifoWrapper
 //	CODING
 //================================================================================
 
-DataFifo	DataFifo
+FifoCtrl FifoCtrl_inst (
+	.ToFifoTxWriteVal_i	(!SmcAwe_i && toFifoVal_i),
+	.ToFifoTxReadVal_i (ToFifoTxReadVal_i),
+	.ToFifoRxWriteVal_i	(ToFifoRxWriteVal_i),
+	.ToFifoRxReadVal_i	(!SmcAre_i),
+	.FifoTxFull_i		(fullFlagTx),
+	.FifoTxEmpty_i		(emptyFlagTx),
+	.FifoRxFull_i		(fullFlagRx),
+	.FifoRxEmpty_i		(emptyFlagRx),
+	.FifoTxWriteEn_o	(txFifoWrEn),
+	.FifoTxReadEn_o		(txFifoRdEn),
+	.FifoRxWriteEn_o	(rxFifoWrEn),
+	.FifoRxReadEn_o		(rxFifoRdEn)
+
+
+
+
+
+);
+
+
+
+DataFifo	DataFifoTx
 ( 
 	.wr_clk		(WrClk_i), 
 	.rd_clk		(RdClk_i), 
 	.din		(ToFifoData_i), 
-	.wr_en		(ToFifoVal_i), 
-	.rd_en		(!SmcAre_i), 
+	.wr_en		(txFifoWrEn), 
+	.rd_en		(txFifoRdEn), 
 	.dout		(ToSpiData_o), 
-	.full		(fullFlag), 
-	.empty		(emptyFlag)
+	.full		(fullFlagTx), 
+	.empty		(emptyFlagTx)
+);
+
+DataFifo	DataFifoRx
+( 
+	.wr_clk		(RdClk_i), 
+	.rd_clk		(WrClk_i), 
+	.din		(ToFifoRxData_i), 
+	.wr_en		(rxFifoWrEn), 
+	.rd_en		(rxFifoRdEn), 
+	.dout		(dataFromRxFifo), 
+	.full		(fullFlagRx), 
+	.empty		(emptyFlagRx)
 );
 
 endmodule

sources_1/new/DataFifo/FifoCtrl.v

@@ -0,0 +1,35 @@
+module FifoCtrl (
+    input ToFifoTxWriteVal_i,
+    input ToFifoTxReadVal_i,
+    input ToFifoRxWriteVal_i,
+    input ToFifoRxReadVal_i,
+
+    input FifoTxFull_i,
+    input FifoTxEmpty_i,
+    input FifoRxFull_i,
+    input FifoRxEmpty_i,
+
+
+    output FifoTxWriteEn_o,
+    output FifoTxReadEn_o,
+    output FifoRxWriteEn_o,
+    output FifoRxReadEn_o
+
+);
+
+
+
+// //================================================================================
+// //	ASSIGNMENTS
+
+assign FifoTxWriteEn_o = ToFifoTxWriteVal_i & ~FifoTxFull_i;
+assign FifoTxReadEn_o = ToFifoTxReadVal_i & ~FifoTxEmpty_i;
+assign FifoRxWriteEn_o = ToFifoRxWriteVal_i & ~FifoRxFull_i;
+assign FifoRxReadEn_o = ToFifoRxReadVal_i & ~FifoRxEmpty_i;
+
+
+
+// //================================================================================
+
+
+endmodule

sources_1/new/MMCM/MmcmWrapper.v

@@ -45,7 +45,7 @@ MMCME2_ADV
    // .CLKIN1_PERIOD       (10.000),
    .CLKIN1_PERIOD       (8.130081300813),
    .CLKIN2_PERIOD       (10.000),
-   .CLKOUT0_DIVIDE_F    (12.3),
+   .CLKOUT0_DIVIDE_F    (15.25),
    .CLKOUT0_DUTY_CYCLE  (0.5),
    .CLKOUT0_PHASE       (0.0),
    .CLKOUT0_USE_FINE_PS ("FALSE"),

sources_1/new/Mux/DataMuxer.v

@@ -35,7 +35,7 @@ module SmcDataMux
     input	Rst_i,
 
 	input	SmcVal_i,
-	input	[CmdRegWidth-1:0]	SmcData_i,
+	input	[CmdRegWidth/2-1:0]	SmcData_i,
     input	[AddrRegWidth-1:0]	SmcAddr_i,
 
 	output	reg	ToRegMapVal_o,
@@ -100,12 +100,8 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 				Fifo2WriteLsbAddr:	begin
 									ToFifoVal_o[2]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*4+:CmdRegWidth]	<=	SmcData_i;
-								end
 				Fifo2WriteMsbAddr:	begin
 									ToFifoVal_o[2]	<=	SmcVal_i;
-									ToFifoData_o[CmdRegWidth*5+:CmdRegWidth]	<=	SmcData_i;
-								end
-				Fifo3WriteLsbAddr:	begin
 									ToFifoVal_o[3]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*6+:CmdRegWidth]	<=	SmcData_i;
 								end
@@ -124,12 +120,8 @@ always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
 				Fifo5WriteLsbAddr:	begin
 									ToFifoVal_o[5]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*10+:CmdRegWidth]	<=	SmcData_i;
-								end
 				Fifo5WriteMsbAddr:	begin
 									ToFifoVal_o[5]	<=	SmcVal_i;
-									ToFifoData_o[CmdRegWidth*11+:CmdRegWidth]	<=	SmcData_i;
-								end
-				Fifo6WriteLsbAddr:	begin
 									ToFifoVal_o[6]	<=	1'b0;
 									ToFifoData_o[CmdRegWidth*12+:CmdRegWidth]	<=	SmcData_i;
 								end

sources_1/new/S5443_3Top.v

@@ -39,7 +39,7 @@ module S5443_3Top
     input SmcAre_i,
     input [1:0] SmcBe_i,
     input SmcAoe_i,
-    output [SpiNum-1:0] LD_i,
+    output [SpiNum-1:0] Ld_i,
 
     output  Led_o,
    
@@ -75,66 +75,66 @@ wire [0:15] baudRate [SpiNum-1:0];
 
 
 //SPI0
-wire [CmdRegWidth-1:0] Spi0Ctrl;
-wire [CmdRegWidth-1:0] Spi0Clk;
-wire [CmdRegWidth-1:0] Spi0CsDelay;
-wire [CmdRegWidth-1:0] Spi0CsCtrl;
-wire [CmdRegWidth-1:0] Spi0TxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi0RxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi0TxFifo;
-wire [CmdRegWidth-1:0] Spi0RxFifo;
+wire [CmdRegWidth-1:0] spi0Ctrl;
+wire [CmdRegWidth-1:0] spi0Clk;
+wire [CmdRegWidth-1:0] spi0CsDelay;
+wire [CmdRegWidth-1:0] spi0CsCtrl;
+wire [CmdRegWidth-1:0] spi0TxFifoCtrl;
+wire [CmdRegWidth-1:0] spi0RxFifoCtrl;
+wire [CmdRegWidth-1:0] spi0TxFifo;
+wire [CmdRegWidth-1:0] spi0RxFifo;
 //SPI1
-wire [CmdRegWidth-1:0] Spi1Ctrl;
-wire [CmdRegWidth-1:0] Spi1Clk;
-wire [CmdRegWidth-1:0] Spi1CsDelay;
-wire [CmdRegWidth-1:0] Spi1CsCtrl;
-wire [CmdRegWidth-1:0] Spi1TxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi1RxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi1TxFifo;
-wire [CmdRegWidth-1:0] Spi1RxFifo;
+wire [CmdRegWidth-1:0] spi1Ctrl;
+wire [CmdRegWidth-1:0] spi1Clk;
+wire [CmdRegWidth-1:0] spi1CsDelay;
+wire [CmdRegWidth-1:0] spi1CsCtrl;
+wire [CmdRegWidth-1:0] spi1TxFifoCtrl;
+wire [CmdRegWidth-1:0] spi1RxFifoCtrl;
+wire [CmdRegWidth-1:0] spi1TxFifo;
+wire [CmdRegWidth-1:0] spi1RxFifo;
 //SPI2
-wire [CmdRegWidth-1:0] Spi2Ctrl;
-wire [CmdRegWidth-1:0] Spi2Clk;
-wire [CmdRegWidth-1:0] Spi2CsDelay;
-wire [CmdRegWidth-1:0] Spi2CsCtrl;
-wire [CmdRegWidth-1:0] Spi2TxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi2RxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi2TxFifo;
+wire [CmdRegWidth-1:0] spi2Ctrl;
+wire [CmdRegWidth-1:0] spi2Clk;
+wire [CmdRegWidth-1:0] spi2CsDelay;
+wire [CmdRegWidth-1:0] spi2CsCtrl;
+wire [CmdRegWidth-1:0] spi2TxFifoCtrl;
+wire [CmdRegWidth-1:0] spi2RxFifoCtrl;
+wire [CmdRegWidth-1:0] spi2TxFifo;
 wire [CmdRegWidth-1:0] Spi2RxFifo;
 //SPI3
-wire [CmdRegWidth-1:0] Spi3Ctrl;
-wire [CmdRegWidth-1:0] Spi3Clk;
-wire [CmdRegWidth-1:0] Spi3CsDelay;
-wire [CmdRegWidth-1:0] Spi3CsCtrl;
-wire [CmdRegWidth-1:0] Spi3TxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi3RxFifoCtrl;
+wire [CmdRegWidth-1:0] spi3Ctrl;
+wire [CmdRegWidth-1:0] spi3Clk;
+wire [CmdRegWidth-1:0] spi3CsDelay;
+wire [CmdRegWidth-1:0] spi3CsCtrl;
+wire [CmdRegWidth-1:0] spi3TxFifoCtrl;
+wire [CmdRegWidth-1:0] spi3RxFifoCtrl;
 wire [CmdRegWidth-1:0] Spi3TxFifo;
 wire [CmdRegWidth-1:0] Spi3RxFifo;
 //SPI4
-wire [CmdRegWidth-1:0] Spi4Ctrl;
-wire [CmdRegWidth-1:0] Spi4Clk;
-wire [CmdRegWidth-1:0] Spi4CsDelay;
-wire [CmdRegWidth-1:0] Spi4CsCtrl;
-wire [CmdRegWidth-1:0] Spi4TxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi4RxFifoCtrl;
+wire [CmdRegWidth-1:0] spi4Ctrl;
+wire [CmdRegWidth-1:0] spi4Clk;
+wire [CmdRegWidth-1:0] spi4CsDelay;
+wire [CmdRegWidth-1:0] spi4CsCtrl;
+wire [CmdRegWidth-1:0] spi4TxFifoCtrl;
+wire [CmdRegWidth-1:0] spi4RxFifoCtrl;
 wire [CmdRegWidth-1:0] Spi4TxFifo;
 wire [CmdRegWidth-1:0] Spi4RxFifo;
 //SPI5
-wire [CmdRegWidth-1:0] Spi5Ctrl;
-wire [CmdRegWidth-1:0] Spi5Clk;
-wire [CmdRegWidth-1:0] Spi5CsDelay;
-wire [CmdRegWidth-1:0] Spi5CsCtrl;
-wire [CmdRegWidth-1:0] Spi5TxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi5RxFifoCtrl;
+wire [CmdRegWidth-1:0] spi5Ctrl;
+wire [CmdRegWidth-1:0] spi5Clk;
+wire [CmdRegWidth-1:0] spi5CsDelay;
+wire [CmdRegWidth-1:0] spi5CsCtrl;
+wire [CmdRegWidth-1:0] spi5TxFifoCtrl;
+wire [CmdRegWidth-1:0] spi5RxFifoCtrl;
 wire [CmdRegWidth-1:0] Spi5TxFifo;
 wire [CmdRegWidth-1:0] Spi5RxFifo;
 //SPI6
-wire [CmdRegWidth-1:0] Spi6Ctrl;
-wire [CmdRegWidth-1:0] Spi6Clk;
-wire [CmdRegWidth-1:0] Spi6CsDelay;
-wire [CmdRegWidth-1:0] Spi6CsCtrl;
-wire [CmdRegWidth-1:0] Spi6TxFifoCtrl;
-wire [CmdRegWidth-1:0] Spi6RxFifoCtrl;
+wire [CmdRegWidth-1:0] spi6Ctrl;
+wire [CmdRegWidth-1:0] spi6Clk;
+wire [CmdRegWidth-1:0] spi6CsDelay;
+wire [CmdRegWidth-1:0] spi6CsCtrl;
+wire [CmdRegWidth-1:0] spi6TxFifoCtrl;
+wire [CmdRegWidth-1:0] spi6RxFifoCtrl;
 wire [CmdRegWidth-1:0] Spi6TxFifo;
 wire [CmdRegWidth-1:0] Spi6RxFifo;
 
@@ -157,14 +157,17 @@ wire [SpiNum-1:0] CPOL;
 wire [SpiNum-1:0] CPHA;
 wire [SpiNum-1:0] endianSel;
 wire [SpiNum-1:0] selSt;
+wire [SpiNum-1:0] spiMode;
+
 
 wire [0:5] stopDelay [SpiNum-1:0];
 wire [SpiNum-1:0] leadx;
-wire [SpiNum-1:0] lagx; 
-wire [SpiNum-1:0] FifoRxRst;
-wire [SpiNum-1:0] FifoTxRst;
-wire [0:7]  WordCntTx [SpiNum-1:0];
-wire [0:7]  WordCntRx [SpiNum-1:0];
+wire [SpiNum-1:0] lag; 
+wire [SpiNum-1:0] fifoRxRst;
+wire [SpiNum-1:0] fifoTxRst;
+wire [0:7]  wordCntTx [SpiNum-1:0];
+wire [0:7]  wordCntRx [SpiNum-1:0];
+
 
 wire [SpiNum-1:0] CS0;
 wire [SpiNum-1:0] CS1;
@@ -177,13 +180,45 @@ wire	[SpiNum-1:0]	spiSyncRst;
 wire	[AddrRegWidth-1:0]	smcAddr;
 wire	[CmdRegWidth/2-1:0]	smcData;
 wire	smcVal;
+//RxFifo 
+wire [0:23] dataToRxFifo [SpiNum-1:0];
+wire [0:7] addrToRxFifo [SpiNum-1:0];
+wire [SpiNum-1:0] valToRxFifo;
+wire [SpiNum-1:0] valToTxFifoRead;
+
+
+// SPI mode choice 
+wire [SpiNum-1:0] SckR; 
+wire [SpiNum-1:0] SsR;
+wire [SpiNum-1:0] Mosi0R;
+wire [SpiNum-1:0] valReg;
+wire [SpiNum-1:0] valToTxR;
+wire [SpiNum-1:0] valToRxR;
+wire [0:31] dataToRxFifoR [SpiNum-1:0];
+
+
+wire [SpiNum-1:0] SckQ;
+wire [SpiNum-1:0] SsQ;
+wire [SpiNum-1:0] Mosi0Q;
+wire [SpiNum-1:0] valToTxQ;
+wire [SpiNum-1:0] valToRxQ;
+wire [0:31] dataToRxFifoQ [SpiNum-1:0];
+wire [0:15] dataFromRxFifo [SpiNum-1:0];
+reg  [15:0] dataFromRxFifoR;
+wire [15:0] dataFromRxFifoW;
+
+
+
+
+
+
+
 	
 wire	[CmdRegWidth/2-1:0]	ansData;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
 assign ten = SpiTxRxEn[6:0];
-assign Mosi0_o = Mosi0;
 assign Mosi1_o = Mosi1;
 assign Mosi2_o = Mosi2;
 assign Mosi3_o = Mosi3;
@@ -203,85 +238,94 @@ assign SsFlash_o[5] = (Assel[5])?(CS1[5]? Ss[5]:~Ss[5]):CS1[5];
 assign SsFlash_o[6] = (Assel[6])?(CS1[6]? Ss[6]:~Ss[6]):CS1[6];
 assign Sck_o = Sck;
 
-assign widthSel[0] = Spi0Ctrl[6:5];
-assign widthSel[1] = Spi1Ctrl[6:5];
-assign widthSel[2] = Spi2Ctrl[6:5];
-assign widthSel[3] = Spi3Ctrl[6:5];
-assign widthSel[4] = Spi4Ctrl[6:5];
-assign widthSel[5] = Spi5Ctrl[6:5];
-assign widthSel[6] = Spi6Ctrl[6:5];
-
-assign CPOL[0] = Spi0Ctrl[2];
-assign CPOL[1] = Spi1Ctrl[2];
-assign CPOL[2] = Spi2Ctrl[2];
-assign CPOL[3] = Spi3Ctrl[2];
-assign CPOL[4] = Spi4Ctrl[2];
-assign CPOL[5] = Spi5Ctrl[2];
-assign CPOL[6] = Spi6Ctrl[2];
-
-assign CPHA[0] = Spi0Ctrl[1];
-assign CPHA[1] = Spi1Ctrl[1];
-assign CPHA[2] = Spi2Ctrl[1];
-assign CPHA[3] = Spi3Ctrl[1];
-assign CPHA[4] = Spi4Ctrl[1];
-assign CPHA[5] = Spi5Ctrl[1];
-assign CPHA[6] = Spi6Ctrl[1];
-
-assign endianSel[0] = Spi0Ctrl[8];
-assign endianSel[1] = Spi1Ctrl[8];
-assign endianSel[2] = Spi2Ctrl[8];
-assign endianSel[3] = Spi3Ctrl[8];
-assign endianSel[4] = Spi4Ctrl[8];
-assign endianSel[5] = Spi5Ctrl[8];
-assign endianSel[6] = Spi6Ctrl[8];
-
-assign selSt[0] = Spi0Ctrl[4];
-assign selSt[1] = Spi1Ctrl[4];
-assign selSt[2] = Spi2Ctrl[4];
-assign selSt[3] = Spi3Ctrl[4];
-assign selSt[4] = Spi4Ctrl[4];
-assign selSt[5] = Spi5Ctrl[4];
-assign selSt[6] = Spi6Ctrl[4];
-
-assign Assel[0] = Spi0Ctrl[3];
-assign Assel[1] = Spi1Ctrl[3];
-assign Assel[2] = Spi2Ctrl[3];
-assign Assel[3] = Spi3Ctrl[3];
-assign Assel[4] = Spi4Ctrl[3];
-assign Assel[5] = Spi5Ctrl[3];
-assign Assel[6] = Spi6Ctrl[3];
-
-assign stopDelay[0] = Spi0CsDelay[7:2];
-assign stopDelay[1] = Spi1CsDelay[7:2];
-assign stopDelay[2] = Spi2CsDelay[7:2];
-assign stopDelay[3] = Spi3CsDelay[7:2];
-assign stopDelay[4] = Spi4CsDelay[7:2];
-assign stopDelay[5] = Spi5CsDelay[7:2];
-assign stopDelay[6] = Spi6CsDelay[7:2];
-
-assign leadx[0] = Spi0CsDelay[1];
-assign leadx[1] = Spi1CsDelay[1];
-assign leadx[2] = Spi2CsDelay[1];
-assign leadx[3] = Spi3CsDelay[1];
-assign leadx[4] = Spi4CsDelay[1];
-assign leadx[5] = Spi5CsDelay[1];
-assign leadx[6] = Spi6CsDelay[1];
-
-assign lagx[0] = Spi0CsDelay[0];
-assign lagx[1] = Spi1CsDelay[0];
-assign lagx[2] = Spi2CsDelay[0];
-assign lagx[3] = Spi3CsDelay[0];
-assign lagx[4] = Spi4CsDelay[0];
-assign lagx[5] = Spi5CsDelay[0];
-assign lagx[6] = Spi6CsDelay[0];
-
-assign baudRate[0] = Spi0Clk[15:0];
-assign baudRate[1] = Spi1Clk[15:0];
-assign baudRate[2] = Spi2Clk[15:0];
-assign baudRate[3] = Spi3Clk[15:0];
-assign baudRate[4] = Spi4Clk[15:0];
-assign baudRate[5] = Spi5Clk[15:0];
-assign baudRate[6] = Spi6Clk[15:0];
+assign widthSel[0] = spi0Ctrl[6:5];
+assign widthSel[1] = spi1Ctrl[6:5];
+assign widthSel[2] = spi2Ctrl[6:5];
+assign widthSel[3] = spi3Ctrl[6:5];
+assign widthSel[4] = spi4Ctrl[6:5];
+assign widthSel[5] = spi5Ctrl[6:5];
+assign widthSel[6] = spi6Ctrl[6:5];
+
+assign spiMode[0] = spi0Ctrl[7];
+assign spiMode[1] = spi1Ctrl[7];
+assign spiMode[2] = spi2Ctrl[7];
+assign spiMode[3] = spi3Ctrl[7];
+assign spiMode[4] = spi4Ctrl[7];
+assign spiMode[5] = spi5Ctrl[7];
+assign spiMode[6] = spi6Ctrl[7];
+
+
+assign CPOL[0] = spi0Ctrl[2];
+assign CPOL[1] = spi1Ctrl[2];
+assign CPOL[2] = spi2Ctrl[2];
+assign CPOL[3] = spi3Ctrl[2];
+assign CPOL[4] = spi4Ctrl[2];
+assign CPOL[5] = spi5Ctrl[2];
+assign CPOL[6] = spi6Ctrl[2];
+
+assign CPHA[0] = spi0Ctrl[1];
+assign CPHA[1] = spi1Ctrl[1];
+assign CPHA[2] = spi2Ctrl[1];
+assign CPHA[3] = spi3Ctrl[1];
+assign CPHA[4] = spi4Ctrl[1];
+assign CPHA[5] = spi5Ctrl[1];
+assign CPHA[6] = spi6Ctrl[1];
+
+assign endianSel[0] = spi0Ctrl[8];
+assign endianSel[1] = spi1Ctrl[8];
+assign endianSel[2] = spi2Ctrl[8];
+assign endianSel[3] = spi3Ctrl[8];
+assign endianSel[4] = spi4Ctrl[8];
+assign endianSel[5] = spi5Ctrl[8];
+assign endianSel[6] = spi6Ctrl[8];
+
+assign selSt[0] = spi0Ctrl[4];
+assign selSt[1] = spi1Ctrl[4];
+assign selSt[2] = spi2Ctrl[4];
+assign selSt[3] = spi3Ctrl[4];
+assign selSt[4] = spi4Ctrl[4];
+assign selSt[5] = spi5Ctrl[4];
+assign selSt[6] = spi6Ctrl[4];
+
+assign Assel[0] = spi0Ctrl[3];
+assign Assel[1] = spi1Ctrl[3];
+assign Assel[2] = spi2Ctrl[3];
+assign Assel[3] = spi3Ctrl[3];
+assign Assel[4] = spi4Ctrl[3];
+assign Assel[5] = spi5Ctrl[3];
+assign Assel[6] = spi6Ctrl[3];
+
+assign stopDelay[0] = spi0CsDelay[7:2];
+assign stopDelay[1] = spi1CsDelay[7:2];
+assign stopDelay[2] = spi2CsDelay[7:2];
+assign stopDelay[3] = spi3CsDelay[7:2];
+assign stopDelay[4] = spi4CsDelay[7:2];
+assign stopDelay[5] = spi5CsDelay[7:2];
+assign stopDelay[6] = spi6CsDelay[7:2];
+
+assign leadx[0] = spi0CsDelay[1];
+assign leadx[1] = spi1CsDelay[1];
+assign leadx[2] = spi2CsDelay[1];
+assign leadx[3] = spi3CsDelay[1];
+assign leadx[4] = spi4CsDelay[1];
+assign leadx[5] = spi5CsDelay[1];
+assign leadx[6] = spi6CsDelay[1];
+
+assign lag[0] = spi0CsDelay[0];
+assign lag[1] = spi1CsDelay[0];
+assign lag[2] = spi2CsDelay[0];
+assign lag[3] = spi3CsDelay[0];
+assign lag[4] = spi4CsDelay[0];
+assign lag[5] = spi5CsDelay[0];
+assign lag[6] = spi6CsDelay[0];
+
+assign baudRate[0] = spi0Clk[15:0];
+assign baudRate[1] = spi1Clk[15:0];
+assign baudRate[2] = spi2Clk[15:0];
+assign baudRate[3] = spi3Clk[15:0];
+assign baudRate[4] = spi4Clk[15:0];
+assign baudRate[5] = spi5Clk[15:0];
+assign baudRate[6] = spi6Clk[15:0];
 
 
 assign SpiRst_o[0] = GPIOA[0];
@@ -292,68 +336,154 @@ assign SpiRst_o[4] = GPIOA[4];
 assign SpiRst_o[5] = GPIOA[5];
 assign SpiRst_o[6] = GPIOA[6];
 
-assign FifoRxRst[0] = Spi0RxFifoCtrl[0];
-assign FifoRxRst[1] = Spi1RxFifoCtrl[0];
-assign FifoRxRst[2] = Spi2RxFifoCtrl[0];
-assign FifoRxRst[3] = Spi3RxFifoCtrl[0];
-assign FifoRxRst[4] = Spi4RxFifoCtrl[0];
-assign FifoRxRst[5] = Spi5RxFifoCtrl[0];
-assign FifoRxRst[6] = Spi6RxFifoCtrl[0];
-
-assign FifoTxRst[0] = Spi0TxFifoCtrl[0];
-assign FifoTxRst[1] = Spi1TxFifoCtrl[0];
-assign FifoTxRst[2] = Spi2TxFifoCtrl[0];
-assign FifoTxRst[3] = Spi3TxFifoCtrl[0];
-assign FifoTxRst[4] = Spi4TxFifoCtrl[0];
-assign FifoTxRst[5] = Spi5TxFifoCtrl[0];
-assign FifoTxRst[6] = Spi6TxFifoCtrl[0];
-
-assign LD_i[0] = GPIOA[16];
-assign LD_i[1] = GPIOA[17];
-assign LD_i[2] = GPIOA[18];
-assign LD_i[3] = GPIOA[19];
-assign LD_i[4] = GPIOA[20];
-assign LD_i[5] = GPIOA[21];
-assign LD_i[6] = GPIOA[22];
-assign LD_o = LD_i[0]&LD_i[1]&LD_i[2]&LD_i[3]&LD_i[4]&LD_i[5]&LD_i[6];
-
-assign WordCntRx[0] = Spi0RxFifoCtrl[15:8];
-assign WordCntRx[1] = Spi1RxFifoCtrl[15:8];
-assign WordCntRx[2] = Spi2RxFifoCtrl[15:8];
-assign WordCntRx[3] = Spi3RxFifoCtrl[15:8];
-assign WordCntRx[4] = Spi4RxFifoCtrl[15:8];
-assign WordCntRx[5] = Spi5RxFifoCtrl[15:8];
-assign WordCntRx[6] = Spi6RxFifoCtrl[15:8];
-
-assign WordCntTx[0] = Spi0TxFifoCtrl[15:8];
-assign WordCntTx[1] = Spi1TxFifoCtrl[15:8];
-assign WordCntTx[2] = Spi2TxFifoCtrl[15:8];
-assign WordCntTx[3] = Spi3TxFifoCtrl[15:8];
-assign WordCntTx[4] = Spi4TxFifoCtrl[15:8];
-assign WordCntTx[5] = Spi5TxFifoCtrl[15:8];
-assign WordCntTx[6] = Spi6TxFifoCtrl[15:8];
-
-
-assign CS0[0] = Spi0CsCtrl[0];
-assign CS0[1] = Spi1CsCtrl[0];
-assign CS0[2] = Spi2CsCtrl[0];
-assign CS0[3] = Spi3CsCtrl[0];
-assign CS0[4] = Spi4CsCtrl[0];
-assign CS0[5] = Spi5CsCtrl[0];
-assign CS0[6] = Spi6CsCtrl[0];
-
-assign CS1[0] = Spi0CsCtrl[1];
-assign CS1[1] = Spi1CsCtrl[1];
-assign CS1[2] = Spi2CsCtrl[1];
-assign CS1[3] = Spi3CsCtrl[1];
-assign CS1[4] = Spi4CsCtrl[1];
-assign CS1[5] = Spi5CsCtrl[1];
-assign CS1[6] = Spi6CsCtrl[1];
+assign fifoRxRst[0] = spi0RxFifoCtrl[0];
+assign fifoRxRst[1] = spi1RxFifoCtrl[0];
+assign fifoRxRst[2] = spi2RxFifoCtrl[0];
+assign fifoRxRst[3] = spi3RxFifoCtrl[0];
+assign fifoRxRst[4] = spi4RxFifoCtrl[0];
+assign fifoRxRst[5] = spi5RxFifoCtrl[0];
+assign fifoRxRst[6] = spi6RxFifoCtrl[0];
+
+assign fifoTxRst[0] = spi0TxFifoCtrl[0];
+assign fifoTxRst[1] = spi1TxFifoCtrl[0];
+assign fifoTxRst[2] = spi2TxFifoCtrl[0];
+assign fifoTxRst[3] = spi3TxFifoCtrl[0];
+assign fifoTxRst[4] = spi4TxFifoCtrl[0];
+assign fifoTxRst[5] = spi5TxFifoCtrl[0];
+assign fifoTxRst[6] = spi6TxFifoCtrl[0];
+
+assign Ld_i[0] = GPIOA[16];
+assign Ld_i[1] = GPIOA[17];
+assign Ld_i[2] = GPIOA[18];
+assign Ld_i[3] = GPIOA[19];
+assign Ld_i[4] = GPIOA[20];
+assign Ld_i[5] = GPIOA[21];
+assign Ld_i[6] = GPIOA[22];
+assign LD_o = Ld_i[0]&Ld_i[1]&Ld_i[2]&Ld_i[3]&Ld_i[4]&Ld_i[5]&Ld_i[6];
+
+assign wordCntRx[0] = spi0RxFifoCtrl[15:8];
+assign wordCntRx[1] = spi1RxFifoCtrl[15:8];
+assign wordCntRx[2] = spi2RxFifoCtrl[15:8];
+assign wordCntRx[3] = spi3RxFifoCtrl[15:8];
+assign wordCntRx[4] = spi4RxFifoCtrl[15:8];
+assign wordCntRx[5] = spi5RxFifoCtrl[15:8];
+assign wordCntRx[6] = spi6RxFifoCtrl[15:8];
+
+assign wordCntTx[0] = spi0TxFifoCtrl[15:8];
+assign wordCntTx[1] = spi1TxFifoCtrl[15:8];
+assign wordCntTx[2] = spi2TxFifoCtrl[15:8];
+assign wordCntTx[3] = spi3TxFifoCtrl[15:8];
+assign wordCntTx[4] = spi4TxFifoCtrl[15:8];
+assign wordCntTx[5] = spi5TxFifoCtrl[15:8];
+assign wordCntTx[6] = spi6TxFifoCtrl[15:8];
+
+
+assign CS0[0] = spi0CsCtrl[0];
+assign CS0[1] = spi1CsCtrl[0];
+assign CS0[2] = spi2CsCtrl[0];
+assign CS0[3] = spi3CsCtrl[0];
+assign CS0[4] = spi4CsCtrl[0];
+assign CS0[5] = spi5CsCtrl[0];
+assign CS0[6] = spi6CsCtrl[0];
+
+assign CS1[0] = spi0CsCtrl[1];
+assign CS1[1] = spi1CsCtrl[1];
+assign CS1[2] = spi2CsCtrl[1];
+assign CS1[3] = spi3CsCtrl[1];
+assign CS1[4] = spi4CsCtrl[1];
+assign CS1[5] = spi5CsCtrl[1];
+assign CS1[6] = spi6CsCtrl[1];
+
+
+assign Ss[0] = (spiMode)? SsQ[0]:SsR[0];
+assign Ss[1] = (spiMode)? SsQ[1]:SsR[1];
+assign Ss[2] = (spiMode)? SsQ[2]:SsR[2];
+assign Ss[3] = (spiMode)? SsQ[3]:SsR[3];
+assign Ss[4] = (spiMode)? SsQ[4]:SsR[4];
+assign Ss[5] = (spiMode)? SsQ[5]:SsR[5];
+assign Ss[6] = (spiMode)? SsQ[6]:SsR[6];
+
+assign Sck[0] = (spiMode)? SckQ[0]:SckR[0];
+assign Sck[1] = (spiMode)? SckQ[1]:SckR[1];
+assign Sck[2] = (spiMode)? SckQ[2]:SckR[2];
+assign Sck[3] = (spiMode)? SckQ[3]:SckR[3];
+assign Sck[4] = (spiMode)? SckQ[4]:SckR[4];
+assign Sck[5] = (spiMode)? SckQ[5]:SckR[5];
+assign Sck[6] = (spiMode)? SckQ[6]:SckR[6];
+
+assign Mosi0[0] = (spiMode)? Mosi0Q[0]:valReg[0];
+assign Mosi0[1] = (spiMode)? Mosi0Q[1]:valReg[1];
+assign Mosi0[2] = (spiMode)? Mosi0Q[2]:valReg[2];
+assign Mosi0[3] = (spiMode)? Mosi0Q[3]:valReg[3];
+assign Mosi0[4] = (spiMode)? Mosi0Q[4]:valReg[4];
+assign Mosi0[5] = (spiMode)? Mosi0Q[5]:valReg[5];
+assign Mosi0[6] = (spiMode)? Mosi0Q[6]:valReg[6];
+
+assign valToTxFifoRead[0] = (spiMode)? valToTxQ[0]:valToTxR[0];
+assign valToTxFifoRead[1] = (spiMode)? valToTxQ[1]:valToTxR[1];
+assign valToTxFifoRead[2] = (spiMode)? valToTxQ[2]:valToTxR[2];
+assign valToTxFifoRead[3] = (spiMode)? valToTxQ[3]:valToTxR[3];
+assign valToTxFifoRead[4] = (spiMode)? valToTxQ[4]:valToTxR[4];
+assign valToTxFifoRead[5] = (spiMode)? valToTxQ[5]:valToTxR[5];
+assign valToTxFifoRead[6] = (spiMode)? valToTxQ[6]:valToTxR[6];
+
+assign valToRxFifo[0] = (spiMode)? valToRxQ[0]:valToRxR[0];
+assign valToRxFifo[1] = (spiMode)? valToRxQ[1]:valToRxR[1];
+assign valToRxFifo[2] = (spiMode)? valToRxQ[2]:valToRxR[2];
+assign valToRxFifo[3] = (spiMode)? valToRxQ[3]:valToRxR[3];
+assign valToRxFifo[4] = (spiMode)? valToRxQ[4]:valToRxR[4];
+assign valToRxFifo[5] = (spiMode)? valToRxQ[5]:valToRxR[5];
+assign valToRxFifo[6] = (spiMode)? valToRxQ[6]:valToRxR[6];
+
+assign dataToRxFifo[0] = (spiMode)? dataToRxFifoQ[0]:dataToRxFifoR[0];
+assign dataToRxFifo[1] = (spiMode)? dataToRxFifoQ[1]:dataToRxFifoR[1];
+assign dataToRxFifo[2] = (spiMode)? dataToRxFifoQ[2]:dataToRxFifoR[2];
+assign dataToRxFifo[3] = (spiMode)? dataToRxFifoQ[3]:dataToRxFifoR[3];
+assign dataToRxFifo[4] = (spiMode)? dataToRxFifoQ[4]:dataToRxFifoR[4];
+assign dataToRxFifo[5] = (spiMode)? dataToRxFifoQ[5]:dataToRxFifoR[5];
+assign dataToRxFifo[6] = (spiMode)? dataToRxFifoQ[6]:dataToRxFifoR[6];
+
+
+assign dataFromRxFifoW =  dataFromRxFifoR;
 
 //================================================================================
 //  CODING
 //================================================================================	
 
+always @(*) begin 
+    if (initRst) begin 
+        dataFromRxFifoR = 16'b0;
+    end
+    else begin 
+        case (Ss_o)  
+            7'b0000001: begin 
+                dataFromRxFifoR = dataFromRxFifo[0];
+            end
+            7'b0000010: begin 
+                dataFromRxFifoR = dataFromRxFifo[1];
+            end
+            7'b0000011: begin 
+                dataFromRxFifoR = dataFromRxFifo[2];
+            end
+            7'b0000100: begin 
+                dataFromRxFifoR = dataFromRxFifo[3];
+            end
+            7'b0000101: begin 
+                dataFromRxFifoR = dataFromRxFifo[4];
+            end
+            7'b0000110: begin 
+                dataFromRxFifoR = dataFromRxFifo[5];
+            end
+            7'b0000111: begin 
+                dataFromRxFifoR = dataFromRxFifo[6];
+            end
+            default: dataFromRxFifoR = 16'b0;
+        endcase
+    end
+end
+
+
+
 BUFG BUFG_inst (
    .O(gclk), // 1-bit output: Clock output
    .I(Clk123_i)  // 1-bit input: Clock input
@@ -413,66 +543,66 @@ RegMap_inst
     .Led_o(Led_o),
     .AnsDataReg_o(ansData),
     //Spi0
-    .Spi0CtrlReg_o(Spi0Ctrl),
-    .Spi0ClkReg_o(Spi0Clk),
-    .Spi0CsDelayReg_o(Spi0CsDelay),
-    .Spi0CsCtrlReg_o(Spi0CsCtrl),
-    .Spi0TxFifoCtrlReg_o(Spi0TxFifoCtrl),
-    .Spi0RxFifoCtrlReg_o(Spi0RxFifoCtrl),
-    .Spi0TxFifoReg_o(Spi0TxFifo),
-    .Spi0RxFifoReg_o(Spi0RxFifo),
+    .Spi0CtrlReg_o(spi0Ctrl),
+    .Spi0ClkReg_o(spi0Clk),
+    .Spi0CsDelayReg_o(spi0CsDelay),
+    .Spi0CsCtrlReg_o(spi0CsCtrl),
+    .Spi0TxFifoCtrlReg_o(spi0TxFifoCtrl),
+    .Spi0RxFifoCtrlReg_o(spi0RxFifoCtrl),
+    .Spi0TxFifoReg_o(spi0TxFifo),
+    .Spi0RxFifoReg_o(spi0RxFifo),
     //Spi1
-    .Spi1CtrlReg_o(Spi1Ctrl),
-    .Spi1ClkReg_o(Spi1Clk),
-    .Spi1CsDelayReg_o(Spi1CsDelay),
-    .Spi1CsCtrlReg_o(Spi1CsCtrl),
-    .Spi1TxFifoCtrlReg_o(Spi1TxFifoCtrl),
-    .Spi1RxFifoCtrlReg_o(Spi1RxFifoCtrl),
-    .Spi1TxFifoReg_o(Spi1TxFifo),
-    .Spi1RxFifoReg_o(Spi1RxFifo),
+    .Spi1CtrlReg_o(spi1Ctrl),
+    .Spi1ClkReg_o(spi1Clk),
+    .Spi1CsDelayReg_o(spi1CsDelay),
+    .Spi1CsCtrlReg_o(spi1CsCtrl),
+    .Spi1TxFifoCtrlReg_o(spi1TxFifoCtrl),
+    .Spi1RxFifoCtrlReg_o(spi1RxFifoCtrl),
+    .Spi1TxFifoReg_o(spi1TxFifo),
+    .Spi1RxFifoReg_o(spi1RxFifo),
     //Spi2
-    .Spi2CtrlReg_o(Spi2Ctrl),
-    .Spi2ClkReg_o(Spi2Clk),
-    .Spi2CsDelayReg_o(Spi2CsDelay),
-    .Spi2CsCtrlReg_o(Spi2CsCtrl),
-    .Spi2TxFifoCtrlReg_o(Spi2TxFifoCtrl),
-    .Spi2RxFifoCtrlReg_o(Spi2RxFifoCtrl),
-    .Spi2TxFifoReg_o(Spi2TxFifo),
+    .Spi2CtrlReg_o(spi2Ctrl),
+    .Spi2ClkReg_o(spi2Clk),
+    .Spi2CsDelayReg_o(spi2CsDelay),
+    .Spi2CsCtrlReg_o(spi2CsCtrl),
+    .Spi2TxFifoCtrlReg_o(spi2TxFifoCtrl),
+    .Spi2RxFifoCtrlReg_o(spi2RxFifoCtrl),
+    .Spi2TxFifoReg_o(spi2TxFifo),
     .Spi2RxFifoReg_o(Spi2RxFifo),
     //Spi3
-    .Spi3CtrlReg_o(Spi3Ctrl),
-    .Spi3ClkReg_o(Spi3Clk),
-    .Spi3CsDelayReg_o(Spi3CsDelay),
-    .Spi3CsCtrlReg_o(Spi3CsCtrl),
-    .Spi3TxFifoCtrlReg_o(Spi3TxFifoCtrl),
-    .Spi3RxFifoCtrlReg_o(Spi3RxFifoCtrl),
+    .Spi3CtrlReg_o(spi3Ctrl),
+    .Spi3ClkReg_o(spi3Clk),
+    .Spi3CsDelayReg_o(spi3CsDelay),
+    .Spi3CsCtrlReg_o(spi3CsCtrl),
+    .Spi3TxFifoCtrlReg_o(spi3TxFifoCtrl),
+    .Spi3RxFifoCtrlReg_o(spi3RxFifoCtrl),
     .Spi3TxFifoReg_o(Spi3TxFifo),
     .Spi3RxFifoReg_o(Spi3RxFifo),
     //Spi4
-    .Spi4CtrlReg_o(Spi4Ctrl),
-    .Spi4ClkReg_o(Spi4Clk),
-    .Spi4CsDelayReg_o(Spi4CsDelay),
-    .Spi4CsCtrlReg_o(Spi4CsCtrl),
-    .Spi4TxFifoCtrlReg_o(Spi4TxFifoCtrl),
-    .Spi4RxFifoCtrlReg_o(Spi4RxFifoCtrl),
+    .Spi4CtrlReg_o(spi4Ctrl),
+    .Spi4ClkReg_o(spi4Clk),
+    .Spi4CsDelayReg_o(spi4CsDelay),
+    .Spi4CsCtrlReg_o(spi4CsCtrl),
+    .Spi4TxFifoCtrlReg_o(spi4TxFifoCtrl),
+    .Spi4RxFifoCtrlReg_o(spi4RxFifoCtrl),
     .Spi4TxFifoReg_o(Spi4TxFifo),
     .Spi4RxFifoReg_o(Spi4RxFifo),
     //Spi5
-    .Spi5CtrlReg_o(Spi5Ctrl),
-    .Spi5ClkReg_o(Spi5Clk),
-    .Spi5CsDelayReg_o(Spi5CsDelay),
-    .Spi5CsCtrlReg_o(Spi5CsCtrl),
-    .Spi5TxFifoCtrlReg_o(Spi5TxFifoCtrl),
-    .Spi5RxFifoCtrlReg_o(Spi5RxFifoCtrl),
+    .Spi5CtrlReg_o(spi5Ctrl),
+    .Spi5ClkReg_o(spi5Clk),
+    .Spi5CsDelayReg_o(spi5CsDelay),
+    .Spi5CsCtrlReg_o(spi5CsCtrl),
+    .Spi5TxFifoCtrlReg_o(spi5TxFifoCtrl),
+    .Spi5RxFifoCtrlReg_o(spi5RxFifoCtrl),
     .Spi5TxFifoReg_o(Spi5TxFifo),
     .Spi5RxFifoReg_o(Spi5RxFifo),
     //Spi6
-    .Spi6CtrlReg_o(Spi6Ctrl),
-    .Spi6ClkReg_o(Spi6Clk),
-    .Spi6CsDelayReg_o(Spi6CsDelay),
-    .Spi6CsCtrlReg_o(Spi6CsCtrl),
-    .Spi6TxFifoCtrlReg_o(Spi6TxFifoCtrl),
-    .Spi6RxFifoCtrlReg_o(Spi6RxFifoCtrl),
+    .Spi6CtrlReg_o(spi6Ctrl),
+    .Spi6ClkReg_o(spi6Clk),
+    .Spi6CsDelayReg_o(spi6CsDelay),
+    .Spi6CsCtrlReg_o(spi6CsCtrl),
+    .Spi6TxFifoCtrlReg_o(spi6TxFifoCtrl),
+    .Spi6RxFifoCtrlReg_o(spi6RxFifoCtrl),
     .Spi6TxFifoReg_o(Spi6TxFifo),
     .Spi6RxFifoReg_o(Spi6RxFifo),
 
@@ -489,6 +619,7 @@ MmcmWrapper MainMmcm
 );
 
 
+
 genvar i;
 
 generate
@@ -509,24 +640,71 @@ generate
 			// .Rst_i		(spiSyncRst[i] | FifoRxRst[i]),
 			.Rst_i		(FifoRxRst[i]),
             .SmcAre_i   (SmcAre_i),
+            .SmcAwe_i   (SmcAwe_i),
 	
 			.ToFifoVal_i	(toFifoVal[i]),
+            .ToFifoRxData_i (dataToRxFifo[i]),
+            .ToFifoRxWriteVal_i (valToRxFifo[i]),
+            .ToFifoTxReadVal_i (valToTxFifoRead[i]),
 			.ToFifoData_i	(toFifoData[32*i+:32]),
+
 			
 			.ToSpiVal_o		(toSpiVal[i]),
+            .DataFromRxFifo_o (dataToRxFifo[i]),
 			.ToSpiData_o	(toSpiData[i])
 		);
-		
+
+
+
+        SPIm SPIm_inst (
+            .Clk_i(spiClkBus[i]),
+            .Start_i(ten[i]),
+            .Rst_i(initRst| spiMode[i]),
+            .SPIdata(toSpiData[i]),
+            .Sck_o(SckR[i]),
+            .Ss_o(SsR[i]),
+            .Mosi0_o(valReg[i]),
+            .WidthSel_i(widthSel[i]),
+            .PulsePol_i(CPOL[i]),
+            .CPHA_i(CPHA[i]),
+            .EndianSel_i(endianSel[i]),
+            .LAG_i(lag[i]),
+            .LEAD_i(leadx[i]),
+            .Stop_i(stopDelay[i]),
+            .SELST_i(selSt[i]),
+            .Val_o(valToTxR[i])
+
+
+
+
+
+
+
+        );
+
+        SPIs SPIs_inst (
+            .Clk_i(spiClkBus[i]),
+            .Rst_i(initRst|SpiRst_o[i]| spiMode[i]),
+            .Sck_i(SckR[i]),
+            .Ss_i(SsR[i]),
+            .Mosi0_i(valReg[i]),
+            .WidthSel_i(widthSel[i]),
+            .SELST_i(selSt[i]),
+            .DataToRxFifo_o(dataToRxFifoR[i]),
+            .Val_o(valToRxR[i])
+        );
+
+
         QuadSPIm QuadSPIm_inst (
             .Clk_i(spiClkBus[i]),
             .Start_i(ten[i]),
-            .Rst_i(initRst),
+            .Rst_i(initRst| !spiMode[i]),
 			.SpiDataVal_i	(toSpiVal),
             // .SPIdata(32'h2aaa00aa),
             .SPIdata(toSpiData[i]),
-            .Sck_o(Sck[i]),
-            .Ss_o(Ss[i]),
-            .Mosi0_i(Mosi0[i]),
+            .Sck_o(SckQ[i]),
+            .Ss_o(SsQ[i]),
+            .Mosi0_i(Mosi0Q[i]),
             .Mosi1_i(Mosi1[i]),
             .Mosi2_i(Mosi2[i]),
             .Mosi3_i(Mosi3[i]),
@@ -534,11 +712,27 @@ generate
             .PulsePol_i(CPOL[i]),
             .CPHA_i(CPHA[i]),
             .EndianSel_i(endianSel[i]),
-            .LAG_i(lagx[i]),
+            .LAG_i(lag[i]),
             .LEAD_i(leadx[i]),
             .Stop_i(stopDelay[i]),
-            .SELST_i(selSt[i])
+            .SELST_i(selSt[i]),
+            .Val_o(valToTxQ[i])
+        );
+        QuadSPIs QuadSPIs_inst (
+            .Clk_i(spiClkBus[i]),
+            .Rst_i(initRst|SpiRst_o[i]| !spiMode[i]),
+            .Sck_i(SckQ[i]),
+            .Ss_i(SsQ[i]),
+            .Mosi0_i(Mosi0[i]),
+            .Mosi1_i(Mosi1[i]),
+            .Mosi2_i(Mosi2[i]),
+            .Mosi3_i(Mosi3[i]),
+            .WidthSel_i(widthSel[i]),
+            .SELST_i(selSt[i]),
+            .DataToRxFifo_o(dataToRxFifoQ[i]),
+            .Val_o(valToRxQ[i])
         );
+
     end
 endgenerate
 

sources_1/new/SpiR/SPIm.v

@@ -0,0 +1,375 @@
+module SPIm (
+    input Clk_i,
+    input Rst_i,
+    input Start_i,
+    input CPHA_i,
+    input [31:0] SPIdata,
+	input SpiDataVal_i,
+    input SELST_i,
+    input [1:0] WidthSel_i,
+    input  LAG_i,
+    input  LEAD_i,
+    input EndianSel_i,
+    input [5:0] Stop_i,
+    input PulsePol_i,
+
+
+    output reg Mosi0_o,
+    output reg Sck_o,
+    output  Ss_o,
+    output  Val_o
+);
+
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+reg startFlag;
+reg startR;
+reg [31:0] trCnt;
+reg valReg;
+reg valToRxFifo1;
+reg [2:0] ssCnt;
+reg Ss;
+reg SSr;
+reg [7:0] mosiReg0;
+reg [3:0] ssNum;
+reg [2:0] delayCnt;
+reg stopFlag;
+
+wire SsPol = SELST_i ? Ss : ~Ss;
+
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+
+
+assign Ss_o = SsPol; 
+
+
+
+assign Val_o = (trCnt < 1 ) ?valToRxFifo1:valReg;
+//================================================================================
+//	CODING
+//================================================================================
+always @(posedge Clk_i) begin 
+    startR <= Start_i;
+end
+
+always @(*) begin 
+    if (Rst_i) begin 
+        valToRxFifo1 = 1'b0;
+    end
+    else begin 
+        if (Start_i && !startR) begin 
+            valToRxFifo1 = 1'b1;
+        end
+        else begin 
+            valToRxFifo1 = 1'b0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        trCnt <= 1'b0;
+    end
+    else begin 
+        if ( (ssNum + LEAD_i + LAG_i)-1) begin 
+            trCnt <= trCnt + 1'b1;
+        end
+    end
+end
+
+
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        delayCnt <= 1'b0;
+    end
+    else begin 
+        if (stopFlag &&delayCnt < Stop_i) begin 
+            delayCnt <= delayCnt + 1'b1;
+        end
+        else begin 
+            delayCnt <= 1'b0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        stopFlag <= 1'b0;
+    end
+    else begin
+        if (SELST_i) begin 
+            if (Ss && !SSr) begin 
+                stopFlag <= 1'b1;
+            end
+            else if ( delayCnt == Stop_i) begin 
+                stopFlag <= 1'b0;
+            end
+        end
+        else begin 
+            if (!Ss && SSr) begin 
+                stopFlag <= 1'b1;
+            end
+            else if (delayCnt == Stop_i) begin 
+                stopFlag <= 1'b0;
+            end
+        end
+    end
+end
+
+
+
+
+always @(*) begin 
+    if (PulsePol_i) begin 
+        if (CPHA_i) begin
+            if (LEAD_i == 0) begin 
+            if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                Sck_o = ~(~Clk_i);
+            end
+            else begin 
+                Sck_o = 1'b0;
+                end
+            end
+            else begin 
+                if (!Ss && (ssCnt < ssNum+LAG_i+LEAD_i && ssCnt > LAG_i)) begin 
+                    Sck_o = ~(~Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+        end
+        else begin
+            if (LEAD_i == 0) begin 
+                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    Sck_o = ~(Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+            else begin 
+                if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    Sck_o = ~(Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+        end
+    end
+    else begin 
+        if (CPHA_i) begin
+            if (LEAD_i == 0) begin  
+                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    Sck_o = ~(Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+            else begin 
+                if (!Ss && (ssCnt <ssNum + LAG_i + LAG_i && ssCnt > LAG_i)) begin 
+                    Sck_o = ~(Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+        end 
+        else begin
+            if (LEAD_i == 0) begin 
+                if (!Ss && (ssCnt <= ssNum+LAG_i+LEAD_i && ssCnt > LAG_i) ) begin 
+                    Sck_o = ~(~Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+            else begin 
+                if (!Ss && (ssCnt < ssNum + LAG_i + LEAD_i && ssCnt > LAG_i)) begin 
+                    Sck_o = ~(~Clk_i);
+                end
+                else begin 
+                    Sck_o = 1'b0;
+                end
+            end
+        end
+    end
+end
+
+
+always @(*) begin
+    if (Rst_i) begin 
+        Mosi0_o = 1'b0;
+    end
+    else begin
+        if (!EndianSel_i) begin 
+            case (WidthSel_i)  
+                0 : begin
+                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[7]):1'b0;
+                end
+                1 : begin
+                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[15]):1'b0;
+                end
+                2 : begin
+                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[23]):1'b0;
+                end
+                3 : begin
+                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[31]):1'b0;
+                end
+            endcase
+        end
+        else begin 
+            case (WidthSel_i)  
+                0 : begin
+                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                end
+                1 : begin
+                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                end
+                2 : begin
+                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                end
+                3 : begin
+                    Mosi0_o = (!Ss&& (ssCnt < ssNum+LAG_i && ssCnt > LAG_i))? (mosiReg0[0]):1'b0;
+                end
+            endcase
+        end
+    end
+end
+
+
+
+
+always @(posedge Clk_i) begin
+    SSr <= Ss;
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin 
+        startFlag = 1'b0;
+    end
+    else begin 
+        if (Start_i && !stopFlag) begin 
+            startFlag = 1'b1;
+        end
+        else begin 
+            startFlag = 1'b0;
+        end
+    end
+end
+
+always @(*) begin
+    if (SELST_i) begin 
+        if (Ss && !SSr) begin 
+            valReg = 1'b1;
+        end
+        else begin 
+            valReg = 1'b0;
+        end
+    end
+    else begin 
+        if (!Ss&& SSr) begin 
+            valReg = 1'b1;
+        end
+        else begin 
+            valReg = 1'b0;
+        end
+    end
+end
+
+always @(*) begin 
+    if (Rst_i) begin 
+        ssNum = 1'b0;
+    end
+    else begin 
+        case (WidthSel_i) 
+            0 : begin 
+                ssNum = 8;
+            end
+            1 : begin 
+                ssNum = 16;
+            end
+            2 : begin 
+                ssNum = 24;
+            end
+            3 : begin 
+                ssNum = 32;
+            end
+        endcase
+    end
+end
+
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        ssCnt <= 1'b0;
+    end
+    else if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag  ) begin 
+        ssCnt <= ssCnt + 1'b1;
+    end
+    else begin
+        if (ssCnt == ssNum-1 || !startFlag) begin 
+            ssCnt <= 1'b0;
+        end
+    end
+end
+
+
+
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        Ss <= 1'b1;
+    end
+    else begin 
+        if (ssCnt < (ssNum+LAG_i+LEAD_i)  && startFlag ) begin 
+            Ss <= 1'b0;
+        end
+        else begin 
+            Ss <= 1'b1;
+        end
+    end
+end
+
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        mosiReg0 <= SPIdata[31:0];
+    end
+    else begin
+        if (!EndianSel_i) begin 
+            if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                mosiReg0 <= mosiReg0 << 1;
+            end
+            else begin 
+                mosiReg0 <= SPIdata[31:0];
+            end
+        end
+        else begin 
+            if (!SSr && (ssCnt > LAG_i && ssCnt < ssNum + LAG_i + LEAD_i)) begin
+                mosiReg0 <= mosiReg0 >> 1;
+            end
+            else begin 
+                mosiReg0 <= SPIdata[31:0];
+            end
+        end
+    end
+end
+
+
+
+
+
+
+
+endmodule

sources_1/new/SpiR/SPIs.v

@@ -0,0 +1,157 @@
+module SPIs (
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi0_i,
+    input [1:0] WidthSel_i,
+    input SELST_i,
+   
+
+    output reg [23:0] Data_o,
+    output reg [7:0] Addr_o,
+    output [31:0] DataToRxFifo_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+
+reg ssReg;
+reg ssRegR;  
+reg [31:0] shiftReg;
+
+reg [31:0] shiftRegM; 
+ 
+
+//===============================================================================
+//  ASSIGNMENTS
+
+
+assign DataToRxFifo_o = {Addr_o, Data_o};
+
+//================================================================================
+//	CODING
+//================================================================================
+
+always	@(posedge	Clk_i)	begin
+	ssReg	<=	Ss_i;
+	ssRegR	<=	ssReg;
+end
+
+
+always @(*) begin 
+    if (Rst_i) begin
+      shiftRegM = 32'h0;
+    end
+    else begin 
+        case(WidthSel_i)  
+             0: begin 
+                shiftRegM = shiftReg[7:0];
+            end
+            1: begin 
+                shiftRegM = shiftReg[15:0];
+            end
+            2: begin 
+                shiftRegM = shiftReg[23:0];
+            end
+            3: begin 
+                shiftRegM = shiftReg[31:0];
+            end
+        endcase
+    end
+end
+
+
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Data_o <= 24'h0;
+    end
+    else begin
+        if (SELST_i) begin  
+            if (ssReg && !ssRegR) begin 
+                Data_o <= shiftRegM;
+            end
+        end
+        else begin 
+            if (!ssReg && ssRegR) begin 
+                Data_o <= shiftRegM[23:0];
+            end
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Addr_o <= 8'h0;
+    end
+    else begin
+        if (SELST_i) begin 
+            if (ssReg && !ssRegR) begin 
+                Addr_o <= shiftRegM[31:24];
+            end
+        end
+        else begin 
+            if (!ssReg && ssRegR) begin 
+                Addr_o <= shiftRegM[31:24];
+            end
+        end
+    end
+end
+
+
+
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        shiftReg<= 32'h0;
+    end
+    else begin
+        if (SELST_i) begin   
+            if (!Ss_i) begin 
+                shiftReg<= {shiftReg[30:0], Mosi0_i};
+            end
+            else begin 
+                shiftReg<= 32'h0;
+            end
+        end
+        else begin 
+            if (Ss_i) begin 
+                shiftReg<= {shiftReg[30:0], Mosi0_i};
+            end
+            else begin 
+                shiftReg<= 32'h0;
+            end
+        end
+    end
+end
+
+
+
+
+always @(posedge Clk_i) begin
+    if (SELST_i) begin 
+        if (ssReg && !ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
+    end
+    else begin 
+        if (!ssReg&& ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
+    end
+end
+
+
+
+
+endmodule