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@@ -30,12 +30,13 @@ module S5443_3Top #(
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input Clk123_i,
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input [AddrRegWidth-2:0] Addr_i,
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inout [CmdRegWidth/2-1:0] Data_i,
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- input [SpiNum-1:0] SpiRst_i,
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+
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input writeEn_i,
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input readEn_i,
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// input DspRst_i,
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input [1:0] BE_i,
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input outputEn_i,
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+ output [SpiNum-1:0] LD_i,
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output Led_o,
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@@ -44,7 +45,9 @@ module S5443_3Top #(
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output [SpiNum-1:0] Mosi2_o,
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output [SpiNum-1:0] Mosi3_o,
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output [SpiNum-1:0] Ss_o,
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- output [SpiNum-1:0] Sck_o
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+ output [SpiNum-1:0] Sck_o,
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+ output [SpiNum-1:0] SpiRst_o,
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+ output LD_o
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);
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@@ -61,10 +64,10 @@ wire [SpiNum-1:0]Mosi3;
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wire [SpiNum-1:0] ten;
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wire clk80;
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wire clk61;
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-wire Rst_i;
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+wire initRst;
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wire gclk;
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-wire [15:0] baudRate [SpiNum-1:0];
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-wire [19:0] baudRateexp;
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+wire [0:15] baudRate [SpiNum-1:0];
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+
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//SPI0
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wire [CmdRegWidth-1:0] Spi0Ctrl;
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@@ -134,6 +137,30 @@ wire [CmdRegWidth-1:0] SpiTxRxEn;
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wire [CmdRegWidth-1:0] GPIOA;
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+wire [AddrRegWidth-1:0] toRegMapAddr;
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+wire [CmdRegWidth-1:0] toRegMapData;
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+wire toRegMapVal;
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+
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+wire [SpiNum-1:0] toFifoVal;
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+wire [CmdRegWidth*SpiNum-1:0] toFifoData;
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+
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+wire [SpiNum-1:0] toSpiVal;
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+wire [CmdRegWidth-1:0] toSpiData;
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+
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+wire [0:1] widthSel [SpiNum-1:0];
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+wire [SpiNum-1:0] CPOL;
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+wire [SpiNum-1:0] CPHA;
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+wire [SpiNum-1:0] endianSel;
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+wire [SpiNum-1:0] selSt;
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+
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+wire [0:5] stopDelay [SpiNum-1:0];
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+wire [SpiNum-1:0] leadx;
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+wire [SpiNum-1:0] lagx;
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+wire [SpiNum-1:0] FifoRxRst;
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+wire [SpiNum-1:0] FifoTxRst;
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+wire [0:7] WordCntTx [SpiNum-1:0];
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+wire [0:7] WordCntRx [SpiNum-1:0];
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+
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//================================================================================
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@@ -148,13 +175,128 @@ assign Mosi2_o = Mosi2;
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assign Mosi3_o = Mosi3;
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assign Ss_o = Ss;
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assign Sck_o = Sck;
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-// assign baudRate[15:0][0] =Spi0Clk[15:0];
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-// assign baudRate[15:0][1] =Spi1Clk[15:0];
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-// assign baudRate[15:0][2] =Spi2Clk[15:0];
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-// assign baudRate[15:0][3] =Spi3Clk[15:0];
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-// assign baudRate[15:0][4] =Spi4Clk[15:0];
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-// assign baudRate[15:0][5] =Spi5Clk[15:0];
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-// assign baudRate[15:0][6] =Spi6Clk[15:0];
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+
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+assign widthSel[0] = Spi0Ctrl[6:5];
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+assign widthSel[1] = Spi1Ctrl[6:5];
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+assign widthSel[2] = Spi2Ctrl[6:5];
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+assign widthSel[3] = Spi3Ctrl[6:5];
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+assign widthSel[4] = Spi4Ctrl[6:5];
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+assign widthSel[5] = Spi5Ctrl[6:5];
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+assign widthSel[6] = Spi6Ctrl[6:5];
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+
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+assign CPOL[0] = Spi0Ctrl[2];
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+assign CPOL[1] = Spi1Ctrl[2];
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+assign CPOL[2] = Spi2Ctrl[2];
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+assign CPOL[3] = Spi3Ctrl[2];
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+assign CPOL[4] = Spi4Ctrl[2];
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+assign CPOL[5] = Spi5Ctrl[2];
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+assign CPOL[6] = Spi6Ctrl[2];
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+
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+assign CPHA[0] = Spi0Ctrl[1];
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+assign CPHA[1] = Spi1Ctrl[1];
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+assign CPHA[2] = Spi2Ctrl[1];
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+assign CPHA[3] = Spi3Ctrl[1];
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+assign CPHA[4] = Spi4Ctrl[1];
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+assign CPHA[5] = Spi5Ctrl[1];
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+assign CPHA[6] = Spi6Ctrl[1];
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+
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+assign endianSel[0] = Spi0Ctrl[8];
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+assign endianSel[1] = Spi1Ctrl[8];
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+assign endianSel[2] = Spi2Ctrl[8];
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+assign endianSel[3] = Spi3Ctrl[8];
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+assign endianSel[4] = Spi4Ctrl[8];
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+assign endianSel[5] = Spi5Ctrl[8];
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+assign endianSel[6] = Spi6Ctrl[8];
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+
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+assign selSt[0] = Spi0Ctrl[4];
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+assign selSt[1] = Spi1Ctrl[4];
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+assign selSt[2] = Spi2Ctrl[4];
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+assign selSt[3] = Spi3Ctrl[4];
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+assign selSt[4] = Spi4Ctrl[4];
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+assign selSt[5] = Spi5Ctrl[4];
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+assign selSt[6] = Spi6Ctrl[4];
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+
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+assign stopDelay[0] = Spi0CsDelay[7:2];
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+assign stopDelay[1] = Spi1CsDelay[7:2];
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+assign stopDelay[2] = Spi2CsDelay[7:2];
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+assign stopDelay[3] = Spi3CsDelay[7:2];
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+assign stopDelay[4] = Spi4CsDelay[7:2];
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+assign stopDelay[5] = Spi5CsDelay[7:2];
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+assign stopDelay[6] = Spi6CsDelay[7:2];
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+
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+assign leadx[0] = Spi0CsDelay[1];
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+assign leadx[1] = Spi1CsDelay[1];
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+assign leadx[2] = Spi2CsDelay[1];
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+assign leadx[3] = Spi3CsDelay[1];
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+assign leadx[4] = Spi4CsDelay[1];
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+assign leadx[5] = Spi5CsDelay[1];
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+assign leadx[6] = Spi6CsDelay[1];
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+
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+assign lagx[0] = Spi0CsDelay[0];
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+assign lagx[1] = Spi1CsDelay[0];
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+assign lagx[2] = Spi2CsDelay[0];
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+assign lagx[3] = Spi3CsDelay[0];
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+assign lagx[4] = Spi4CsDelay[0];
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+assign lagx[5] = Spi5CsDelay[0];
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+assign lagx[6] = Spi6CsDelay[0];
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+
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+assign baudRate[0] = Spi0Clk[15:0];
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+assign baudRate[1] = Spi1Clk[15:0];
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+assign baudRate[2] = Spi2Clk[15:0];
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+assign baudRate[3] = Spi3Clk[15:0];
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+assign baudRate[4] = Spi4Clk[15:0];
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+assign baudRate[5] = Spi5Clk[15:0];
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+assign baudRate[6] = Spi6Clk[15:0];
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+
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+
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+assign SpiRst_o[0] = GPIOA[0];
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+assign SpiRst_o[1] = GPIOA[1];
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+assign SpiRst_o[2] = GPIOA[2];
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+assign SpiRst_o[3] = GPIOA[3];
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+assign SpiRst_o[4] = GPIOA[4];
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+assign SpiRst_o[5] = GPIOA[5];
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+assign SpiRst_o[6] = GPIOA[6];
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+
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+assign FifoRxRst[0] = Spi0RxFifoCtrl[0];
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+assign FifoRxRst[1] = Spi1RxFifoCtrl[0];
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+assign FifoRxRst[2] = Spi2RxFifoCtrl[0];
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+assign FifoRxRst[3] = Spi3RxFifoCtrl[0];
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+assign FifoRxRst[4] = Spi4RxFifoCtrl[0];
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+assign FifoRxRst[5] = Spi5RxFifoCtrl[0];
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+assign FifoRxRst[6] = Spi6RxFifoCtrl[0];
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+
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+assign FifoTxRst[0] = Spi0TxFifoCtrl[0];
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+assign FifoTxRst[1] = Spi1TxFifoCtrl[0];
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+assign FifoTxRst[2] = Spi2TxFifoCtrl[0];
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+assign FifoTxRst[3] = Spi3TxFifoCtrl[0];
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+assign FifoTxRst[4] = Spi4TxFifoCtrl[0];
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+assign FifoTxRst[5] = Spi5TxFifoCtrl[0];
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+assign FifoTxRst[6] = Spi6TxFifoCtrl[0];
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+
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+assign LD_i[0] = GPIOA[16];
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+assign LD_i[1] = GPIOA[17];
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+assign LD_i[2] = GPIOA[18];
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+assign LD_i[3] = GPIOA[19];
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+assign LD_i[4] = GPIOA[20];
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+assign LD_i[5] = GPIOA[21];
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+assign LD_i[6] = GPIOA[22];
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+assign LD_o = LD_i[0]&LD_i[1]&LD_i[2]&LD_i[3]&LD_i[4]&LD_i[5]&LD_i[6];
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+
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+assign WordCntRx[0] = Spi0RxFifoCtrl[15:8];
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+assign WordCntRx[1] = Spi1RxFifoCtrl[15:8];
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+assign WordCntRx[2] = Spi2RxFifoCtrl[15:8];
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+assign WordCntRx[3] = Spi3RxFifoCtrl[15:8];
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+assign WordCntRx[4] = Spi4RxFifoCtrl[15:8];
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+assign WordCntRx[5] = Spi5RxFifoCtrl[15:8];
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+assign WordCntRx[6] = Spi6RxFifoCtrl[15:8];
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+
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+assign WordCntTx[0] = Spi0TxFifoCtrl[15:8];
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+assign WordCntTx[1] = Spi1TxFifoCtrl[15:8];
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+assign WordCntTx[2] = Spi2TxFifoCtrl[15:8];
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+assign WordCntTx[3] = Spi3TxFifoCtrl[15:8];
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+assign WordCntTx[4] = Spi4TxFifoCtrl[15:8];
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+assign WordCntTx[5] = Spi5TxFifoCtrl[15:8];
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+assign WordCntTx[6] = Spi6TxFifoCtrl[15:8];
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//================================================================================
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@@ -167,7 +309,7 @@ BUFG BUFG_inst (
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);
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- clk_wiz_0 ClkGen
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+ clk_wiz_0 ClkGen
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(
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.s_axi_aclk (), // input s_axi_aclk
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.s_axi_aresetn (), // input s_axi_aresetn,
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@@ -190,11 +332,30 @@ BUFG BUFG_inst (
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.s_axi_rready (), // input s_axi_rready,
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// Clock out ports
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.clk_out1(Clk100_i), // output clk_out1
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+ // .clk_out2(clk61), // output clk_out2
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// Status and control signals
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.locked(), // output locked
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// Clock in ports
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.clk_in1(gclk)); // input clk_in1
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+SmcDataMux SmcDataMuxer
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+(
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+ .Clk_i (gclk),
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+ .Rst_i (initRst),
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+
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+ .SmcVal_i (1'b1),
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+ .SmcData_i ({Data_i,Data_i}),
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+ .SmcAddr_i ({Addr_i,1'b0}),
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+
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+ .ToRegMapVal_o (toRegMapVal),
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+ .ToRegMapData_o (toRegMapData),
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+ .ToRegMapAddr_o (toRegMapAddr),
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+
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+ .ToFifoVal_o (toFifoVal),
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+ .ToFifoData_o (toFifoData)
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+
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+);
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+
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RegMap #(
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.CmdRegWidth(32),
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@@ -202,10 +363,10 @@ RegMap #(
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)
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RegMap_inst (
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.Clk_i(gclk),
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- .Rst_i(Rst_i),
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- .Data_i(Data_i),
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- .Addr_i(addr),
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- .wrEn_i(writeEn_i),
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+ .Rst_i(initRst),
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+ .Data_i(toRegMapData),
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+ .Addr_i(toRegMapAddr),
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+ .wrEn_i(writeEn_i|toRegMapVal),
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.rdEn_i(readEn_i),
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.BE_i(BE_i),
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.Led_o(Led_o),
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@@ -286,23 +447,42 @@ genvar i;
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generate
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for (i = 0; i < SpiNum; i = i + 1) begin: SpiGen
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+
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+ DataFifoWrapper DataFifoWrapepr
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+ (
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+ .WrClk_i (gclk),
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+ .RdClk_i (Clk100_i),
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+ .Rst_i (initRst | FifoRxRst[i]),
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+ .readEn_i (readEn_i),
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+
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+ .ToFifoVal_i (toFifoVal[i]),
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+ .ToFifoData_i (toFifoData[32*i+:32]),
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+
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+ .ToSpiVal_o (toSpiVal[i]),
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+ .ToSpiData_o (toSpiData[i])
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+ );
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+
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QuadSPIm QuadSPIm_inst (
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.Clk_i(Clk100_i),
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.Start_i(ten[i]),
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- .Rst_i(Rst_i|SpiRst_i[i]),
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- .SPIdata(32'h2aaa00aa),
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+ .Rst_i(initRst),
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+ .SpiDataVal_i (toSpiVal),
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+ // .SPIdata(32'h2aaa00aa),
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+ .SPIdata(toSpiData[i]),
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.Sck_o(Sck[i]),
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.Ss_o(Ss[i]),
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.Mosi0_i(Mosi0[i]),
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.Mosi1_i(Mosi1[i]),
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.Mosi2_i(Mosi2[i]),
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.Mosi3_i(Mosi3[i]),
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- .WidthSel_i(3),
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- .PulsePol_i(0),
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- .EndianSel_i(1),
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- .LAG_i(0),
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- .LEAD_i(0),
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- .SELST_i(1)
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+ .WidthSel_i(widthSel[i]),
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+ .PulsePol_i(CPOL[i]),
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+ .CPHA_i(CPHA[i]),
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+ .EndianSel_i(endianSel[i]),
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+ .LAG_i(lagx[i]),
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+ .LEAD_i(leadx[i]),
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+ .Stop_i(stopDelay[i]),
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+ .SELST_i(selSt[i])
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);
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end
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endgenerate
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@@ -310,7 +490,7 @@ endgenerate
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InitRst InitRst_inst (
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.clk_i(gclk),
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- .signal_o(Rst_i)
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+ .signal_o(initRst)
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);
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Anatoliy Chigirinskiy