Добавлено вычитывание сигнала LockDetected от устройств.

sources_1/new/RegMap/RegMap.v

@@ -26,6 +26,8 @@ module RegMap #(
     input [CmdRegWidth-1:0] TxFifoCtrlReg6_i,
     input [CmdRegWidth-1:0] RxFifoCtrlReg6_i,
 
+    input [6:0] LdReg_i,
+
 
 
 
@@ -993,7 +995,7 @@ module RegMap #(
     				ansReg = GPIOAReg;
     			end
                 GPIOCtrlAddrS : begin 
-                    ansReg = GPIOARegS;
+                    ansReg = {9'd0,LdReg_i};
                 end
     			Debug0Addr : begin 
     				ansReg = ledReg;

sources_1/new/S5443_3Top.v

@@ -25,7 +25,7 @@ module S5443_3Top
     parameter CmdRegWidth = 32,
     parameter AddrRegWidth = 12,
     parameter STAGES = 3,
-    parameter SpiNum = 1
+    parameter SpiNum = 7
 
 )
 (
@@ -39,7 +39,7 @@ module S5443_3Top
     input SmcAre_i,
     input [1:0] SmcBe_i,
     input SmcAoe_i,
-    output [SpiNum-1:0] Ld_o,
+    input [SpiNum-1:0] Ld_i,
 
     output  Led_o,
    
@@ -286,6 +286,8 @@ module S5443_3Top
 
     wire [SpiNum-1:0] spiEn;
 
+    wire [SpiNum-1:0] ldReg;
+
 
     reg [SpiNum-1:0] ssReg;
     reg [SpiNum-1:0] ssFlashReg;
@@ -460,14 +462,7 @@ module S5443_3Top
     assign fifoTxRst[5] = spi5TxFifoCtrlRR[0];
     assign fifoTxRst[6] = spi6TxFifoCtrlRR[0];
     
-    assign Ld_o[0] = GPIOA[16];
-    assign Ld_o[1] = GPIOA[17];
-    assign Ld_o[2] = GPIOA[18];
-    assign Ld_o[3] = GPIOA[19];
-    assign Ld_o[4] = GPIOA[20];
-    assign Ld_o[5] = GPIOA[21];
-    assign Ld_o[6] = GPIOA[22];
-    assign LD_o = Ld_o[0]&Ld_o[1]&Ld_o[2]&Ld_o[3]&Ld_o[4]&Ld_o[5]&Ld_o[6];
+    assign LD_o = ldReg[0]&ldReg[1]&ldReg[2]&ldReg[3]&ldReg[4]&ldReg[5]&ldReg[6];
     
     assign wordCntRx[0] = spi0RxFifoCtrlRR[15:8];
     assign wordCntRx[1] = spi1RxFifoCtrlRR[15:8];
@@ -748,6 +743,8 @@ module S5443_3Top
         .RxFifoCtrlReg5_i(spi5RxFifoCtrlReg),
         .RxFifoCtrlReg6_i(spi6RxFifoCtrlReg),
 
+        .LdReg_i(ldReg),
+
         //Spi0
         .Spi0CtrlReg_o(spi0Ctrl),
         .Spi0ClkReg_o(spi0Clk),
@@ -836,6 +833,20 @@ module S5443_3Top
                 .signal_o(initRstGen[i])
             );
 
+            xpm_cdc_single #(
+                .DEST_SYNC_FF(3),
+                .INIT_SYNC_FF(0),
+                .SIM_ASSERT_CHK(0),
+                .SRC_INPUT_REG(1)
+            )
+            xpm_cdc_single_inst(
+                .dest_out(ldReg[i]),
+
+                .dest_clk(gclk),
+                .src_clk(spiClkBus[i]),
+                .src_in(Ld_i[i])
+            );
+
             Sync1bit#(
                 .WIDTH(1),
                 .STAGES(STAGES)