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@@ -9,26 +9,32 @@ input clk4out,
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input clk5out,
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input clk6out,
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-output reg clkOutMMCM
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+output ClkOutMMCM_o
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);
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+reg clkOutMMCMReg;
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+
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+wire clkOutMMCM;
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+
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+assign clkOutMMCM = clkOutMMCMReg;
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+
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always @(*) begin
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if (Rst_i) begin
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- clkOutMMCM = 0;
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+ clkOutMMCMReg = 0;
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end
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else begin
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case (clkNum)
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- 0: clkOutMMCM = clk0out;
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- 1: clkOutMMCM = clk1out;
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- 2: clkOutMMCM = clk2out;
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- 3: clkOutMMCM = clk3out;
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- 4: clkOutMMCM = clk4out;
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- 5: clkOutMMCM = clk5out;
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- 6: clkOutMMCM = clk6out;
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- default: clkOutMMCM = 0;
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+ 0: clkOutMMCMReg = clk0out;
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+ 1: clkOutMMCMReg = clk1out;
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+ 2: clkOutMMCMReg = clk2out;
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+ 3: clkOutMMCMReg = clk3out;
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+ 4: clkOutMMCMReg = clk4out;
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+ 5: clkOutMMCMReg = clk5out;
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+ 6: clkOutMMCMReg = clk6out;
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+ default: clkOutMMCMReg = 0;
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endcase
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end
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end
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@@ -36,6 +42,14 @@ end
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+BUFG BUFG_inst (
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+ .O(ClkOutMMCM_o), // 1-bit output: Clock output
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+ .I(clkOutMMCM) // 1-bit input: Clock input
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+);
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+
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+
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+
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+
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endmodule
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