module AdcInitRst (
    clk_i,
    rst_i,

    signal_o,
    done_o
);

//================================================================================
//
//  FUNCTIONS
//
//================================================================================

    function integer bit_num;
        input integer value;
        begin
            bit_num = 0;
            while (value > 0) begin
                value   = value >> 1;
                bit_num = bit_num + 1;
            end
        end
    endfunction

//================================================================================
//
//  PARAMETER/LOCALPARAM
//
//================================================================================

    parameter   DELAY_VALUE     = 24000;
    parameter   LENGTH_WIDTH    = 2;

    localparam  DELAY_CNT_W = bit_num(DELAY_VALUE);

//================================================================================
//
//  PORTS
//
//================================================================================

    input           clk_i;
    input           rst_i;
    output  reg     signal_o;
    output  reg     done_o;

//================================================================================
//
//  STATE MACHINE STATES
//
//================================================================================

    localparam  [1:0]   SM_RST_S    = 2'b00;
    localparam  [1:0]   SM_DELAY_S  = 2'b01;
    localparam  [1:0]   SM_SIGNAL_S = 2'b10;
    localparam  [1:0]   SM_DONE_S   = 2'b11;

//================================================================================
//
//  REG/WIRE
//
//================================================================================

    reg     [1:0]               curr_state;
    reg     [1:0]               next_state;

    reg     [DELAY_CNT_W-1:0]   delay_cnt;
    reg     [DELAY_CNT_W-1:0]   delay_cnt_next;
    reg                         signal_next;
    reg                         done_next;

//================================================================================
//
//  CODING
//
//================================================================================

always @(posedge clk_i or posedge rst_i) begin
    if (rst_i) begin
        curr_state  <= SM_RST_S;
        delay_cnt   <= {DELAY_CNT_W{1'b0}};
        signal_o    <= 1'b0;
        done_o      <= 1'b0;
    end else begin
        curr_state  <= next_state;
        delay_cnt   <= delay_cnt_next;
        signal_o    <= signal_next;
        done_o      <= done_next;
    end
end

always @(*) begin
    next_state      = SM_RST_S;
    delay_cnt_next  = {DELAY_CNT_W{1'b0}};
    signal_next     = 1'b0;
    done_next       = 1'b0;
    case(curr_state)
        SM_RST_S    : begin
            next_state  = SM_DELAY_S;
        end

        SM_DELAY_S  : begin
            if (delay_cnt == DELAY_VALUE[DELAY_CNT_W-1:0]) begin
                next_state      = SM_SIGNAL_S;
                delay_cnt_next  = {DELAY_CNT_W{1'b0}};
            end else begin
                next_state      = SM_DELAY_S;
                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
            end
        end

        SM_SIGNAL_S : begin
            signal_next = 1'b1;
            if (delay_cnt == LENGTH_WIDTH[DELAY_CNT_W-1:0]) begin
                next_state      = SM_DONE_S;
            end else begin
                next_state      = SM_SIGNAL_S;
                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
            end
        end

        SM_DONE_S   : begin
            done_next   = 1'b1;
            next_state  = SM_DONE_S;
        end
    endcase
end

endmodule