module FifoCtrl (
    input ToFifoTxWriteVal_i,
    input ToFifoTxReadVal_i,
    input ToFifoRxWriteVal_i,
    input ToFifoRxReadVal_i,

    input FifoTxFull_i,
    input FifoTxEmpty_i,
    input FifoRxFull_i,
    input FifoRxEmpty_i,


    input FifoTxWrClock_i,
    input FifoTxRdClock_i,
    input FifoRxWrClock_i,
    input FifoRxRdClock_i,

    output FifoTxWriteEn_o,
    output FifoTxReadEn_o,
    output FifoRxWriteEn_o,
    output FifoRxReadEn_o

);


reg FifoTxWriteEn;
reg FifoTxReadEn;
reg FifoRxWriteEn;
reg FifoRxReadEn;



// //================================================================================
// //	ASSIGNMENTS

assign FifoTxWriteEn_o = FifoTxWriteEn;
assign FifoTxReadEn_o = FifoTxReadEn;
assign FifoRxWriteEn_o = FifoRxWriteEn;
assign FifoRxReadEn_o = FifoRxReadEn;



// //================================================================================



always @(posedge FifoTxWrClock_i) begin 
    if (ToFifoTxWriteVal_i && !FifoTxFull_i) begin 
        FifoTxWriteEn <= 1'b1;
    end
    else begin 
        FifoTxWriteEn <= 1'b0;
    end
end

always @(posedge FifoTxRdClock_i ) begin 
    if (ToFifoTxReadVal_i && !FifoTxEmpty_i) begin 
        FifoTxReadEn <= 1'b1;
    end
    else begin 
        FifoTxReadEn <= 1'b0;
    end
end

always @(posedge FifoRxWrClock_i) begin 
    if (ToFifoRxWriteVal_i && !FifoRxFull_i) begin 
        FifoRxWriteEn <= 1'b1;
    end
    else begin 
        FifoRxWriteEn <= 1'b0;
    end
end

always @(posedge FifoRxRdClock_i) begin 
    if (ToFifoRxReadVal_i && !FifoRxEmpty_i) begin 
        FifoRxReadEn <= 1'b1;
    end
    else begin 
        FifoRxReadEn <= 1'b0;
    end
end

// //================================================================================

endmodule