module DataOutMux ( input Rst_i, input Clk_i, input [11:0] Addr_i, input [11:0] ToRegMapAddr_i, input [15:0] DataFromRegMap_i, input [31:0] DataFromRxFifo1_i, input [31:0] DataFromRxFifo2_i, input [31:0] DataFromRxFifo3_i, input [31:0] DataFromRxFifo4_i, input [31:0] DataFromRxFifo5_i, input [31:0] DataFromRxFifo6_i, input [31:0] DataFromRxFifo7_i, output [15:0] AnsData_o ); wire [0:31] dataFromRxFifo [6:0]; wire [15:0] dataFromRegMap; reg [15:0] dataFromRxFifoR; assign dataFromRxFifo[0] = DataFromRxFifo1_i; assign dataFromRxFifo[1] = DataFromRxFifo2_i; assign dataFromRxFifo[2] = DataFromRxFifo3_i; assign dataFromRxFifo[3] = DataFromRxFifo4_i; assign dataFromRxFifo[4] = DataFromRxFifo5_i; assign dataFromRxFifo[5] = DataFromRxFifo6_i; assign dataFromRxFifo[6] = DataFromRxFifo7_i; assign dataFromRegMap = DataFromRegMap_i; assign AnsData_o = (ToRegMapAddr_i)?dataFromRegMap:dataFromRxFifoR; always @(*) begin case (Addr_i) 12'h1c: begin dataFromRxFifoR = DataFromRxFifo1_i[15:0]; end 12'h1e: begin dataFromRxFifoR = DataFromRxFifo1_i[31:16]; end 12'h6c: begin dataFromRxFifoR = DataFromRxFifo2_i[15:0]; end 12'h6e: begin dataFromRxFifoR = DataFromRxFifo2_i[31:16]; end 12'h10c: begin dataFromRxFifoR = DataFromRxFifo3_i[15:0]; end 12'h10e: begin dataFromRxFifoR = DataFromRxFifo1_i[31:16]; end 12'h15c: begin dataFromRxFifoR = DataFromRxFifo4_i[15:0]; end 12'h15e: begin dataFromRxFifoR = DataFromRxFifo4_i[31:16]; end 12'h1ac: begin dataFromRxFifoR = DataFromRxFifo5_i[15:0]; end 12'h1ae: begin dataFromRxFifoR = DataFromRxFifo5_i[31:16]; end 12'h1fc: begin dataFromRxFifoR = DataFromRxFifo6_i[15:0]; end 12'h1fe: begin dataFromRxFifoR = DataFromRxFifo6_i[31:16]; end 12'h24c: begin dataFromRxFifoR = DataFromRxFifo7_i[15:0]; end 12'h24e: begin dataFromRxFifoR = DataFromRxFifo7_i[31:16]; end endcase end endmodule