`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 10.10.2018 01:07:38
// Design Name: 
// Module Name: sram_ctrl2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module	SmcRx
#(
	parameter	DataOutWidth	=	16,
	parameter	DataInWidth		=	16,
	parameter	AddrWidth		=	12
)
(
	input	Clk_i,                       
	input	RstN_i,                     
	input	ForceRstN_i,                     

	input	[DataInWidth-1:0]	SmcD_i,
	input	[AddrWidth-1:0]	SmcA_i,
	input	SmcAwe_i,
	input	SmcAmsN_i,
	input	SmcAoe_i,
	input	SmcAre_i,	
	input	[1:0]	SmcBe_i,	
	
	output	[DataOutWidth-1:0]	Data_o,
	output	[AddrWidth-1:0]	Addr_o,
	output	Val_o
);

//================================================================================
//  REG/WIRE
	
	reg	[AddrWidth-1:0]	smcAddr;
	reg	[DataInWidth-1:0]	smcData;
	reg	val;
	reg	valReg;
	
	reg	smcAwe;
	reg	smcAweR;
	reg	smcAweRR;
	
	reg	smcAmsN;
	reg	smcAmsNR;
	
	wire	smcAweNeg	=	(!smcAweRR&smcAweR);
	
	
	reg	[DataOutWidth-1:0]	dataOutReg;
	reg	[AddrWidth-1:0]		addrDataReg;

//================================================================================
//  LOCALPARAM

//================================================================================
//  ASSIGNMENTS	
	assign	Data_o	=	dataOutReg;
	assign	Addr_o	=	addrDataReg;
	assign	Val_o	=	valReg;
	
	
//================================================================================
//  CODING
	
always	@(posedge	Clk_i)	begin
	if	(RstN_i&ForceRstN_i)	begin
		smcAmsN		<=	SmcAmsN_i;
		smcAmsNR	<=	smcAmsN;
		
		smcAwe		<=	SmcAwe_i;
		smcAweR		<=	smcAwe;
		smcAweRR	<=	smcAweR;
	end	else	begin
		smcAmsN		<=	0;
		smcAmsNR	<=	0;
		
		smcAwe		<=	0;
		smcAweR		<=	0;
		smcAweRR	<=	0;
	end
end
	
always	@(posedge	Clk_i)	begin
	if	(RstN_i&ForceRstN_i)	begin
		if	(!smcAmsNR)	begin
			if	(smcAweNeg)	begin
				smcData	<=	SmcD_i;
				smcAddr	<=	SmcA_i;
				val		<=	1;
			end	else	begin
				val		<=	0;
			end
		end
	end	else	begin
		smcData	<=	0;
		smcAddr	<=	0;
		val		<=	0;
	end
end

always	@(posedge	Clk_i)	begin
	if	(RstN_i&ForceRstN_i)	begin
		if	(val)	begin
			addrDataReg	<=	smcAddr;
			dataOutReg	<=	{dataOutReg[DataInWidth-1:0],smcData};
			valReg	<=	val;
		end	else	begin
			valReg	<=	1'b0;
		end
	end	else	begin
		dataOutReg	<=	0;
		addrDataReg	<=	0;
		valReg	<=	1'b0;
	end
end

endmodule