`timescale 1ns / 1ps
module QuadSPIs_tb ();

reg Clk70_i;
reg Clk50_i;
wire Sck_i;
wire Rst_i;

reg[7:0] mosiReg0_tb;
reg[7:0] mosiReg1_tb;
reg[7:0] mosiReg2_tb;
reg[7:0] mosiReg3_tb;


reg [7:0] Mosi0_i;
reg [7:0] Mosi1_i;
reg [7:0] Mosi2_i;
reg [7:0] Mosi3_i;
reg EnEdge_i;
reg Ss;
reg SSr;
reg SSm;
reg Start_i;
reg startFlag;
reg [5:0] ssCnt; 
reg [3:0] ssNum;
reg [1:0] WidthSel_i;

reg [31:0] SPIdata;


// assign Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
// assign Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
// assign Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
// assign Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
assign Sck_i = (!Ss) ? (Clk70_i) : 1'b0;




// always #(24.390243902439/2) Clk70_i = ~Clk70_i;// 41Mhz
always #(14.285714285714/2) Clk70_i = ~Clk70_i;// 70Mhz
// always #10 Clk70_i = ~Clk70_i;// 50 Mhz

always #10 Clk50_i = ~Clk50_i;




always @(*) begin 
    case (WidthSel_i) 
        0 : begin 
            Mosi0_i = (!Ss) ? (mosiReg3_tb[1]):1'b0;
            Mosi1_i = (!Ss) ? (mosiReg2_tb[1]):1'b0;
            Mosi2_i = (!Ss) ? (mosiReg1_tb[1]):1'b0;
            Mosi3_i = (!Ss) ? (mosiReg0_tb[1]):1'b0;
        end
        1 : begin 
            Mosi0_i = (!Ss) ? (mosiReg3_tb[3]):1'b0;
            Mosi1_i = (!Ss) ? (mosiReg2_tb[3]):1'b0;
            Mosi2_i = (!Ss) ? (mosiReg1_tb[3]):1'b0;
            Mosi3_i = (!Ss) ? (mosiReg0_tb[3]):1'b0;
        end
        2 : begin 
            Mosi0_i = (!Ss) ? (mosiReg3_tb[5]):1'b0;
            Mosi1_i = (!Ss) ? (mosiReg2_tb[5]):1'b0;
            Mosi2_i = (!Ss) ? (mosiReg1_tb[5]):1'b0;
            Mosi3_i = (!Ss) ? (mosiReg0_tb[5]):1'b0;
        end
        3 : begin 
            Mosi0_i = (!Ss) ? (mosiReg3_tb[7]):1'b0;
            Mosi1_i = (!Ss) ? (mosiReg2_tb[7]):1'b0;
            Mosi2_i = (!Ss) ? (mosiReg1_tb[7]):1'b0;
            Mosi3_i = (!Ss) ? (mosiReg0_tb[7]):1'b0;
        end
    endcase
end







initial begin 
    Clk70_i = 1'b1;
    // Clk70_i = 1'b0;//50 Mhz out of phase with src clk
    Clk50_i = 1'b1;
    Start_i = 1'b0;
    EnEdge_i = 1'b1;
    SPIdata = {1'h0, 7'h2a, 8'haa,8'h00,8'haa};
    WidthSel_i = 2'b11;
    #100Start_i = 1'b1;
    #500 Start_i = 1'b0;
    #600 Start_i = 1'b1;
     SPIdata = {1'h1, 7'h29, 24'd520050};
    #100 Start_i = 1'b0;
    #1500 Start_i = 1'b1;
     SPIdata = {1'h0, 7'h2a, 24'd10};
    #100 Start_i = 1'b0;

end


always @(posedge Clk70_i) begin
    if (Rst_i) begin
        SSr <=1'b0;
    end
    else begin 
        SSr <= Ss;
    end
end


always @(posedge Clk70_i) begin 
    if (Rst_i) begin 
        startFlag <= 1'b0;
    end
    else begin 
        if (!Start_i) begin 
            startFlag <= 1'b1;
        end
        else begin 
            startFlag <= 1'b0;
        end
    end
end


always @(*) begin 
    if (Rst_i) begin 
        ssNum = 1'b0;
    end
    else begin 
        case (WidthSel_i) 
            0 : begin 
                ssNum = 2;
            end
            1 : begin 
                ssNum = 4;
            end
            2 : begin 
                ssNum = 6;
            end
            3 : begin 
                ssNum = 8;
            end
        endcase
    end
end


always @(posedge Clk70_i) begin 
    if (Rst_i) begin 
        ssCnt <= 1'b0;
    end
    else if (ssCnt < ssNum && startFlag  ) begin 
        ssCnt <= ssCnt + 1'b1;
    end
    else begin
        if (ssCnt == ssNum-1 || !startFlag) begin 
            ssCnt <= 1'b0;
        end
    end
end

always @(negedge Clk70_i) begin 
    if (Rst_i) begin 
        Ss <= 1'b1;
    end
    else begin 
        if (ssCnt < ssNum && startFlag ) begin 
            Ss <= 1'b0;
        end
        else begin 
            Ss <= 1'b1;
        end
    end
end


always @(negedge Clk70_i) begin 
    if (Rst_i) begin 
        mosiReg0_tb <= SPIdata[31:24];
    end
    else begin 
        if (!SSr) begin
            mosiReg0_tb <= { mosiReg0_tb[6:0],1'b0 };
        end
        else begin 
            mosiReg0_tb <= SPIdata[31:24];
        end
    end
end

always @(negedge Clk70_i) begin 
    if (Rst_i) begin 
        mosiReg1_tb <= SPIdata[23:16];
    end
    else begin 
        if (!SSr) begin
            mosiReg1_tb <= { mosiReg1_tb[6:0],1'b0 };
        end
        else begin 
            mosiReg1_tb <= SPIdata[23:16];
        end
    end
end

always @(negedge Clk70_i) begin 
    if (Rst_i) begin 
        mosiReg2_tb <= SPIdata[15:8];
    end
    else begin 
        if (!SSr) begin
            mosiReg2_tb <= { mosiReg2_tb[6:0],1'b0 };
        end
        else begin 
            mosiReg2_tb <= SPIdata[15:8];
        end
    end
end

always @(negedge Clk70_i) begin 
    if (Rst_i) begin 
        mosiReg3_tb <= SPIdata[7:0];
    end
    else begin 
        if (!SSr) begin
            mosiReg3_tb <= { mosiReg3_tb[6:0],1'b0 };
        end
        else begin 
            mosiReg3_tb <= SPIdata[7:0];
        end
    end
end






QuadSPIs QuadSPI_inst (
    .Sck_i(Sck_i),
    .Clk_i(Clk50_i),
    .Rst_i(Rst_i),
    .Ss_i(Ss),
    .WidthSel_i(WidthSel_i),
    .Mosi0_i(Mosi0_i),
    .Mosi1_i(Mosi1_i),
    .Mosi2_i(Mosi2_i),
    .Mosi3_i(Mosi3_i),
    .EnEdge_i(EnEdge_i),
    .PulsePol_i(1'b0)

);



InitRst InitRst_inst (
    .clk_i(Clk50_i),
    .signal_o(Rst_i)

);










endmodule