`timescale 1ns / 1ps
module SRAM_tb;

reg Clk123;
reg Clk50;
wire Rst_i;
reg writeEn_i;
reg readEn_i;
reg Start_i;


reg [27:0] sramData;

wire [15:0] sramDataOut;
wire [11:0] sramAddrOut;
wire fullFlag;
wire emptyFlag;


reg [4:0] cnt; 
reg [2:0] trCnt;
reg SS;
reg outputEn_i;




assign sramDataOut =sramData[15:0];
// assign sramDataOut = (!outputEn_i)?16'bz:sramData[15:0];
assign sramAddrOut = sramData[27:16];




always #(4.065) Clk123 = ~Clk123;
always #(10) Clk50 = ~Clk50;


initial begin 
    Clk123 = 1'b1;
    Clk50 = 1'b1;
    Start_i = 1'b0;
    #1500 Start_i = 1'b1;
    #500 Start_i = 1'b0;
end





always @(posedge Clk123) begin 
    if (Rst_i) begin 
        cnt <= 1'b0;
    end
    else begin  
        if (cnt < 20 ) begin 
            cnt <= cnt + 1'b1;
        end
        else begin 
            cnt <= 1'b0;
        end
    end
end


always @(posedge Clk123) begin 
    if (Rst_i) begin 
        trCnt <= 1'b0;
    end
    else begin 
        if (cnt == 20 ) begin 
            trCnt <= trCnt + 1'b1;
        end
    end
end


always @(posedge Clk123) begin 
    if (Rst_i) begin 
        sramData <= 28'h00000000;
    end
    else begin 
        case (trCnt) 
            0 : begin 
                sramData <= {11'h0, 16'h01};
            end
            1 : begin 
                sramData <= {11'h02, 16'h00};
            end
        endcase
    end
end




always @(negedge Clk123) begin 
    if (Rst_i) begin 
        SS <= 1'b1;
    end
    else begin 
        if ( cnt >= 0 && cnt !== 9 ) begin 
            SS <= 1'b0;
        end
        else begin 
            SS <= 1'b1;
        end
    end
end



always @(negedge Clk123) begin 
    if (Rst_i) begin 
        writeEn_i <= 1'b1;
    end
    else begin 
        if (cnt >= 2 && cnt <= 6 ) begin 
            writeEn_i <= 1'b0;
        end
        else begin 
            writeEn_i <= 1'b1;
        end
    end
end


always @(negedge Clk123) begin 
    if (Rst_i) begin 
        outputEn_i <= 1'b1;
    end
    else begin 
        if (cnt >= 10 && cnt <= 19 ) begin 
            outputEn_i <= 1'b0;
        end
        else begin 
            outputEn_i <= 1'b1;
        end
    end
end


always @(negedge Clk123) begin 
    if (Rst_i) begin 
        readEn_i <= 1'b1;
    end
    else begin 
        if ((cnt >= 13 && cnt <= 18) ) begin 
            readEn_i <= 1'b0;
        end
        else begin 
            readEn_i <= 1'b1;
        end
    end
end




// always @(posedge Clk_i) begin 
//     if (Rst_i) begin 
//         CE_i <= 1'b0;
//     end
//     else begin
//         if (!fullFlag && ) begin
//             CE_i <= 1'b1;
//         end
//         else begin
//             CE_i <= 1'b0;
//         end
//     end
// end


SRAMr SRAMr_inst (
    .Clk123_i(Clk123),
    // .Clk50_i(Clk50),
    // .Rst_i(Rst_i),
    // .Start_i(Start_i),
    .Addr_i(sramAddrOut),
    .Data_i(),
    .writeEn_i(writeEn_i),
    .readEn_i(readEn_i)
    // .fullFlag(fullFlag),
    // .emptyFlag(emptyFlag),

);




InitRst InitRst_inst (
    .clk_i(Clk123),
    .signal_o(Rst_i)

);









endmodule