module clkOutMMCM(
input Rst_i,
input [2:0]clkNum,
input clk0out,
input clk1out,
input clk2out,
input clk3out,
input clk4out,
input clk5out,
input clk6out, 

output   ClkOutMMCM_o

);


reg clkOutMMCMReg;

wire clkOutMMCM;

assign clkOutMMCM = clkOutMMCMReg;


always @(*) begin 
    if (Rst_i) begin 
        clkOutMMCMReg = 0;
    end
    else begin 
        case (clkNum) 
            0: clkOutMMCMReg = clk0out;
            1: clkOutMMCMReg = clk1out;
            2: clkOutMMCMReg = clk2out;
            3: clkOutMMCMReg = clk3out;
            4: clkOutMMCMReg = clk4out;
            5: clkOutMMCMReg = clk5out;
            6: clkOutMMCMReg = clk6out;
            default: clkOutMMCMReg = 0;
        endcase
    end
end




BUFG BUFG_inst (
   .O(ClkOutMMCM_o), // 1-bit output: Clock output
   .I(clkOutMMCM)  // 1-bit input: Clock input
);






endmodule