`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 10/30/2023 11:24:31 AM // Design Name: // Module Name: S5443_3Top // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module S5443_3Top #( parameter CmdRegWidth = 32, parameter AddrRegWidth = 12, parameter STAGES = 2, parameter SpiNum = 7 ) ( input Clk123_i, input [AddrRegWidth-2:0] SmcAddr_i, inout [CmdRegWidth/2-1:0] SmcData_io, input SmcAwe_i, input SmcAmsN_i, input SmcAre_i, input [1:0] SmcBe_i, input SmcAoe_i, output [SpiNum-1:0] Ld_o, output Led_o, output [SpiNum-1:0] Mosi0_o, inout [SpiNum-1:0] Mosi1_io,//inout: when RSPI mode, input; when QSPI mode output; output [SpiNum-1:0] Mosi2_o, output [SpiNum-1:0] Mosi3_o, output [SpiNum-1:0] Ss_o, output [SpiNum-1:0] SsFlash_o, output [SpiNum-1:0] Sck_o, output [SpiNum-1:0] SpiRst_o, output [SpiNum-1:0] SpiDir_o, output LD_o ); //================================================================================ // REG/WIRE //================================================================================ wire clk80; wire [SpiNum-1:0]sckMuxed; wire [AddrRegWidth-1:0] addrExt; wire [SpiNum-1:0] ssMuxed; wire [SpiNum-1:0]mosi0; wire [SpiNum-1:0]mosi1; wire [SpiNum-1:0]mosi2; wire [SpiNum-1:0]mosi3; wire [SpiNum-1:0] txEn; wire [SpiNum-1:0] spiTxEnSync; wire initRst; wire gclk; wire [0:7] baudRate [SpiNum-1:0]; wire [0:31] txFifoCtrlReg [SpiNum-1:0]; wire [0:31] rxFifoCtrlReg [SpiNum-1:0]; //InitRst wire [SpiNum-1:0] initRstGen; wire rst80; //SPI0 wire [CmdRegWidth-1:0] spi0Ctrl; wire [CmdRegWidth-1:0] spi0Clk; wire [CmdRegWidth-1:0] spi0CsDelay; wire [CmdRegWidth-1:0] spi0CsCtrl; wire [CmdRegWidth-1:0] spi0TxFifoCtrl; wire [CmdRegWidth-1:0] spi0RxFifoCtrl; wire [CmdRegWidth-1:0] spi0TxFifo; wire [CmdRegWidth-1:0] spi0RxFifo; wire [CmdRegWidth-1:0] spi0TxFifoCtrlReg; wire [CmdRegWidth-1:0] spi0RxFifoCtrlReg; wire [CmdRegWidth-1:0] spi0CtrlRR; wire [CmdRegWidth-1:0] spi0ClkRR; wire [CmdRegWidth-1:0] spi0CsDelayRR; wire [CmdRegWidth-1:0] spi0CsCtrlRR; wire [CmdRegWidth-1:0] spi0TxFifoCtrlRR; wire [CmdRegWidth-1:0] spi0RxFifoCtrlRR; //SPI1 wire [CmdRegWidth-1:0] spi1Ctrl; wire [CmdRegWidth-1:0] spi1Clk; wire [CmdRegWidth-1:0] spi1CsDelay; wire [CmdRegWidth-1:0] spi1CsCtrl; wire [CmdRegWidth-1:0] spi1TxFifoCtrl; wire [CmdRegWidth-1:0] spi1RxFifoCtrl; wire [CmdRegWidth-1:0] spi1TxFifoCtrlReg; wire [CmdRegWidth-1:0] spi1RxFifoCtrlReg; wire [CmdRegWidth-1:0] spi1CtrlRR; wire [CmdRegWidth-1:0] spi1CsDelayRR; wire [CmdRegWidth-1:0] spi1CsCtrlRR; wire [CmdRegWidth-1:0] spi1TxFifoCtrlRR; wire [CmdRegWidth-1:0] spi1RxFifoCtrlRR; //SPI2 wire [CmdRegWidth-1:0] spi2Ctrl; wire [CmdRegWidth-1:0] spi2Clk; wire [CmdRegWidth-1:0] spi2CsDelay; wire [CmdRegWidth-1:0] spi2CsCtrl; wire [CmdRegWidth-1:0] spi2TxFifoCtrl; wire [CmdRegWidth-1:0] spi2RxFifoCtrl; wire [CmdRegWidth-1:0] spi2TxFifoCtrlReg; wire [CmdRegWidth-1:0] spi2RxFifoCtrlReg; wire [CmdRegWidth-1:0] spi2CtrlRR; wire [CmdRegWidth-1:0] spi2CsDelayRR; wire [CmdRegWidth-1:0] spi2CsCtrlRR; wire [CmdRegWidth-1:0] spi2TxFifoCtrlRR; wire [CmdRegWidth-1:0] spi2RxFifoCtrlRR; //SPI3 wire [CmdRegWidth-1:0] spi3Ctrl; wire [CmdRegWidth-1:0] spi3Clk; wire [CmdRegWidth-1:0] spi3CsDelay; wire [CmdRegWidth-1:0] spi3CsCtrl; wire [CmdRegWidth-1:0] spi3TxFifoCtrl; wire [CmdRegWidth-1:0] spi3RxFifoCtrl; wire [CmdRegWidth-1:0] spi3TxFifoCtrlReg; wire [CmdRegWidth-1:0] spi3RxFifoCtrlReg; wire [CmdRegWidth-1:0] spi3CtrlRR; wire [CmdRegWidth-1:0] spi3ClkRR; wire [CmdRegWidth-1:0] spi3CsDelayRR; wire [CmdRegWidth-1:0] spi3CsCtrlRR; wire [CmdRegWidth-1:0] spi3TxFifoCtrlRR; wire [CmdRegWidth-1:0] spi3RxFifoCtrlRR; //SPI4 wire [CmdRegWidth-1:0] spi4Ctrl; wire [CmdRegWidth-1:0] spi4Clk; wire [CmdRegWidth-1:0] spi4CsDelay; wire [CmdRegWidth-1:0] spi4CsCtrl; wire [CmdRegWidth-1:0] spi4TxFifoCtrl; wire [CmdRegWidth-1:0] spi4RxFifoCtrl; wire [CmdRegWidth-1:0] spi4TxFifoCtrlReg; wire [CmdRegWidth-1:0] spi4RxFifoCtrlReg; wire [CmdRegWidth-1:0] spi4CtrlRR; wire [CmdRegWidth-1:0] spi4ClkRR; wire [CmdRegWidth-1:0] spi4CsDelayRR; wire [CmdRegWidth-1:0] spi4CsCtrlRR; wire [CmdRegWidth-1:0] spi4TxFifoCtrlRR; wire [CmdRegWidth-1:0] spi4RxFifoCtrlRR; //SPI5 wire [CmdRegWidth-1:0] spi5Ctrl; wire [CmdRegWidth-1:0] spi5Clk; wire [CmdRegWidth-1:0] spi5CsDelay; wire [CmdRegWidth-1:0] spi5CsCtrl; wire [CmdRegWidth-1:0] spi5TxFifoCtrl; wire [CmdRegWidth-1:0] spi5RxFifoCtrl; wire [CmdRegWidth-1:0] spi5TxFifoCtrlReg; wire [CmdRegWidth-1:0] spi5RxFifoCtrlReg; wire [CmdRegWidth-1:0] spi5CtrlRR; wire [CmdRegWidth-1:0] spi5ClkRR; wire [CmdRegWidth-1:0] spi5CsDelayRR; wire [CmdRegWidth-1:0] spi5CsCtrlRR; wire [CmdRegWidth-1:0] spi5TxFifoCtrlRR; wire [CmdRegWidth-1:0] spi5RxFifoCtrlRR; //SPI6 wire [CmdRegWidth-1:0] spi6Ctrl; wire [CmdRegWidth-1:0] spi6Clk; wire [CmdRegWidth-1:0] spi6CsDelay; wire [CmdRegWidth-1:0] spi6CsCtrl; wire [CmdRegWidth-1:0] spi6TxFifoCtrl; wire [CmdRegWidth-1:0] spi6RxFifoCtrl; wire [CmdRegWidth-1:0] spi6TxFifoCtrlReg; wire [CmdRegWidth-1:0] spi6RxFifoCtrlReg; wire [CmdRegWidth-1:0] spi6CtrlRR; wire [CmdRegWidth-1:0] spi6ClkRR; wire [CmdRegWidth-1:0] spi6CsDelayRR; wire [CmdRegWidth-1:0] spi6CsCtrlRR; wire [CmdRegWidth-1:0] spi6TxFifoCtrlRR; wire [CmdRegWidth-1:0] spi6RxFifoCtrlRR; wire [CmdRegWidth-1:0] spiTxRxEn; wire [CmdRegWidth-1:0] GPIOA; wire [CmdRegWidth-1:0] GPIOASync; wire [AddrRegWidth-1:0] toRegMapAddr; wire [CmdRegWidth/2-1:0] toRegMapData; wire toRegMapVal; wire [SpiNum-1:0] toFifoVal; wire [CmdRegWidth*SpiNum-1:0] toFifoData; wire [SpiNum-1:0] toSpiVal; wire [0:31] toSpiData [SpiNum-1:0]; wire [0:1] widthSel [SpiNum-1:0]; wire [SpiNum-1:0] clockPol; wire [SpiNum-1:0] clockPhase; wire [SpiNum-1:0] endianSel; wire [SpiNum-1:0] selSt; wire [SpiNum-1:0] spiMode; wire [0:5] stopDelay [SpiNum-1:0]; wire [SpiNum-1:0] leadx; wire [SpiNum-1:0] lag; wire [SpiNum-1:0] fifoRxRst; wire [SpiNum-1:0] fifoTxRst; wire [SpiNum-1:0] fifoRxRstRdPtr; wire [SpiNum-1:0] fifoTxRstWrPtr; wire [0:7] wordCntTx [SpiNum-1:0]; wire [0:7] wordCntRx [SpiNum-1:0]; wire [SpiNum-1:0] chipSelFpga; wire [SpiNum-1:0] chipSelFlash; wire [SpiNum-1:0] assel; wire [SpiNum-1:0] spiClkBus; wire [SpiNum-1:0] spiSyncRst; wire [AddrRegWidth-1:0] smcAddr; wire [CmdRegWidth/2-1:0] smcData; wire smcVal; //RxFifo wire [0:31] dataToRxFifo [SpiNum-1:0]; wire [0:7] addrToRxFifo [SpiNum-1:0]; wire [SpiNum-1:0] valToRxFifo; wire [SpiNum-1:0] valToTxFifoRead; // SPI mode choice wire [SpiNum-1:0] sckR; wire [SpiNum-1:0] ssR; wire [SpiNum-1:0] mosi0R; wire [SpiNum-1:0] valReg; wire [SpiNum-1:0] valToTxR; wire [SpiNum-1:0] valToRxR; wire [0:31] dataToRxFifoR [SpiNum-1:0]; wire [SpiNum-1:0] sckQ; wire [SpiNum-1:0] ssQ; wire [SpiNum-1:0] mosi0Q; wire [SpiNum-1:0] valToTxQ; wire [SpiNum-1:0] valToRxQ; wire [0:31] dataToRxFifoQ [SpiNum-1:0]; wire [0:31] dataFromRxFifo [SpiNum-1:0]; wire [CmdRegWidth/2-1:0] muxedData; wire smcValComb; wire [CmdRegWidth/2-1:0] ansData; //================================================================================ // ASSIGNMENTS //================================================================================ assign addrExt = {SmcAddr_i, 1'b0}; assign smcValComb = (!SmcAmsN_i && !SmcAwe_i) ? 1'b1 : 1'b0; assign txEn = spiTxRxEn[6:0]; assign Mosi1_io[0] =(SpiDir_o[0])?mosi1[0]:1'bz; assign Mosi1_io[1] =(SpiDir_o[1])?mosi1[1]:1'bz; assign Mosi1_io[2] =(SpiDir_o[2])?mosi1[2]:1'bz; assign Mosi1_io[3] =(SpiDir_o[3])?mosi1[3]:1'bz; assign Mosi1_io[4] =(SpiDir_o[4])?mosi1[4]:1'bz; assign Mosi1_io[5] =(SpiDir_o[5])?mosi1[5]:1'bz; assign Mosi1_io[6] =(SpiDir_o[6])?mosi1[6]:1'bz; assign Mosi2_o = mosi2; assign Mosi3_o = mosi3; assign Ss_o[0] = (assel[0])? ((chipSelFpga[0])? ssMuxed[0]:~ssMuxed[0]):chipSelFpga[0]; assign Ss_o[1] = (assel[1])? ((chipSelFpga[1])? ssMuxed[1]:~ssMuxed[1]):chipSelFpga[1]; assign Ss_o[2] = (assel[2])? ((chipSelFpga[2])? ssMuxed[2]:~ssMuxed[2]):chipSelFpga[2]; assign Ss_o[3] = (assel[3])? ((chipSelFpga[3])? ssMuxed[3]:~ssMuxed[3]):chipSelFpga[3]; assign Ss_o[4] = (assel[4])? ((chipSelFpga[4])? ssMuxed[4]:~ssMuxed[4]):chipSelFpga[4]; assign Ss_o[5] = (assel[5])? ((chipSelFpga[5])? ssMuxed[5]:~ssMuxed[5]):chipSelFpga[5]; assign Ss_o[6] = (assel[6])? ((chipSelFpga[6])? ssMuxed[6]:~ssMuxed[6]):chipSelFpga[6]; assign SsFlash_o[0] = (assel[0])?(chipSelFlash[0]? ssMuxed[0]:~ssMuxed[0]):chipSelFlash[0]; assign SsFlash_o[1] = (assel[1])?(chipSelFlash[1]? ssMuxed[1]:~ssMuxed[1]):chipSelFlash[1]; assign SsFlash_o[2] = (assel[2])?(chipSelFlash[2]? ssMuxed[2]:~ssMuxed[2]):chipSelFlash[2]; assign SsFlash_o[3] = (assel[3])?(chipSelFlash[3]? ssMuxed[3]:~ssMuxed[3]):chipSelFlash[3]; assign SsFlash_o[4] = (assel[4])?(chipSelFlash[4]? ssMuxed[4]:~ssMuxed[4]):chipSelFlash[4]; assign SsFlash_o[5] = (assel[5])?(chipSelFlash[5]? ssMuxed[5]:~ssMuxed[5]):chipSelFlash[5]; assign SsFlash_o[6] = (assel[6])?(chipSelFlash[6]? ssMuxed[6]:~ssMuxed[6]):chipSelFlash[6]; assign Sck_o = sckMuxed; assign widthSel[0] = spi0CtrlRR[6:5]; assign widthSel[1] = spi1CtrlRR[6:5]; assign widthSel[2] = spi2CtrlRR[6:5]; assign widthSel[3] = spi3CtrlRR[6:5]; assign widthSel[4] = spi4CtrlRR[6:5]; assign widthSel[5] = spi5CtrlRR[6:5]; assign widthSel[6] = spi6CtrlRR[6:5]; assign spiMode[0] = spi0CtrlRR[7]; assign spiMode[1] = spi1CtrlRR[7]; assign spiMode[2] = spi2CtrlRR[7]; assign spiMode[3] = spi3CtrlRR[7]; assign spiMode[4] = spi4CtrlRR[7]; assign spiMode[5] = spi5CtrlRR[7]; assign spiMode[6] = spi6CtrlRR[7]; assign clockPol[0] = spi0CtrlRR[2]; assign clockPol[1] = spi1CtrlRR[2]; assign clockPol[2] = spi2CtrlRR[2]; assign clockPol[3] = spi3CtrlRR[2]; assign clockPol[4] = spi4CtrlRR[2]; assign clockPol[5] = spi5CtrlRR[2]; assign clockPol[6] = spi6CtrlRR[2]; assign clockPhase[0] = spi0CtrlRR[1]; assign clockPhase[1] = spi1CtrlRR[1]; assign clockPhase[2] = spi2CtrlRR[1]; assign clockPhase[3] = spi3CtrlRR[1]; assign clockPhase[4] = spi4CtrlRR[1]; assign clockPhase[5] = spi5CtrlRR[1]; assign clockPhase[6] = spi6CtrlRR[1]; assign endianSel[0] = spi0CtrlRR[8]; assign endianSel[1] = spi1CtrlRR[8]; assign endianSel[2] = spi2CtrlRR[8]; assign endianSel[3] = spi3CtrlRR[8]; assign endianSel[4] = spi4CtrlRR[8]; assign endianSel[5] = spi5CtrlRR[8]; assign endianSel[6] = spi6CtrlRR[8]; assign selSt[0] = spi0CtrlRR[4]; assign selSt[1] = spi1CtrlRR[4]; assign selSt[2] = spi2CtrlRR[4]; assign selSt[3] = spi3CtrlRR[4]; assign selSt[4] = spi4CtrlRR[4]; assign selSt[5] = spi5CtrlRR[4]; assign selSt[6] = spi6CtrlRR[4]; assign assel[0] = spi0CtrlRR[3]; assign assel[1] = spi1CtrlRR[3]; assign assel[2] = spi2CtrlRR[3]; assign assel[3] = spi3CtrlRR[3]; assign assel[4] = spi4CtrlRR[3]; assign assel[5] = spi5CtrlRR[3]; assign assel[6] = spi6CtrlRR[3]; assign stopDelay[0] = spi0CsDelayRR[7:2]; assign stopDelay[1] = spi1CsDelayRR[7:2]; assign stopDelay[2] = spi2CsDelayRR[7:2]; assign stopDelay[3] = spi3CsDelayRR[7:2]; assign stopDelay[4] = spi4CsDelayRR[7:2]; assign stopDelay[5] = spi5CsDelayRR[7:2]; assign stopDelay[6] = spi6CsDelayRR[7:2]; assign leadx[0] = spi0CsDelayRR[1]; assign leadx[1] = spi1CsDelayRR[1]; assign leadx[2] = spi2CsDelayRR[1]; assign leadx[3] = spi3CsDelayRR[1]; assign leadx[4] = spi4CsDelayRR[1]; assign leadx[5] = spi5CsDelayRR[1]; assign leadx[6] = spi6CsDelayRR[1]; assign lag[0] = spi0CsDelayRR[0]; assign lag[1] = spi1CsDelayRR[0]; assign lag[2] = spi2CsDelayRR[0]; assign lag[3] = spi3CsDelayRR[0]; assign lag[4] = spi4CsDelayRR[0]; assign lag[5] = spi5CsDelayRR[0]; assign lag[6] = spi6CsDelayRR[0]; assign baudRate[0] = spi0Clk[7:0]; assign baudRate[1] = spi1Clk[7:0]; assign baudRate[2] = spi2Clk[7:0]; assign baudRate[3] = spi3Clk[7:0]; assign baudRate[4] = spi4Clk[7:0]; assign baudRate[5] = spi5Clk[7:0]; assign baudRate[6] = spi6Clk[7:0]; assign SpiRst_o[0] = GPIOASync[0]; assign SpiRst_o[1] = GPIOASync[1]; assign SpiRst_o[2] = GPIOASync[2]; assign SpiRst_o[3] = GPIOASync[3]; assign SpiRst_o[4] = GPIOASync[4]; assign SpiRst_o[5] = GPIOASync[5]; assign SpiRst_o[6] = GPIOASync[6]; assign fifoRxRstRdPtr[0] = spi0RxFifoCtrl[0]; assign fifoRxRstRdPtr[1] = spi1RxFifoCtrl[0]; assign fifoRxRstRdPtr[2] = spi2RxFifoCtrl[0]; assign fifoRxRstRdPtr[3] = spi3RxFifoCtrl[0]; assign fifoRxRstRdPtr[4] = spi4RxFifoCtrl[0]; assign fifoRxRstRdPtr[5] = spi5RxFifoCtrl[0]; assign fifoRxRstRdPtr[6] = spi6RxFifoCtrl[0]; assign fifoRxRst[0] = spi0RxFifoCtrlRR[0]; assign fifoRxRst[1] = spi1RxFifoCtrlRR[0]; assign fifoRxRst[2] = spi2RxFifoCtrlRR[0]; assign fifoRxRst[3] = spi3RxFifoCtrlRR[0]; assign fifoRxRst[4] = spi4RxFifoCtrlRR[0]; assign fifoRxRst[5] = spi5RxFifoCtrlRR[0]; assign fifoRxRst[6] = spi6RxFifoCtrlRR[0]; assign fifoTxRstWrPtr[0] = spi0TxFifoCtrl[0]; assign fifoTxRstWrPtr[1] = spi1TxFifoCtrl[0]; assign fifoTxRstWrPtr[2] = spi2TxFifoCtrl[0]; assign fifoTxRstWrPtr[3] = spi3TxFifoCtrl[0]; assign fifoTxRstWrPtr[4] = spi4TxFifoCtrl[0]; assign fifoTxRstWrPtr[5] = spi5TxFifoCtrl[0]; assign fifoTxRstWrPtr[6] = spi6TxFifoCtrl[0]; assign fifoTxRst[0] = spi0TxFifoCtrlRR[0]; assign fifoTxRst[1] = spi1TxFifoCtrlRR[0]; assign fifoTxRst[2] = spi2TxFifoCtrlRR[0]; assign fifoTxRst[3] = spi3TxFifoCtrlRR[0]; assign fifoTxRst[4] = spi4TxFifoCtrlRR[0]; assign fifoTxRst[5] = spi5TxFifoCtrlRR[0]; assign fifoTxRst[6] = spi5TxFifoCtrlRR[0]; assign Ld_o[0] = GPIOA[16]; assign Ld_o[1] = GPIOA[17]; assign Ld_o[2] = GPIOA[18]; assign Ld_o[3] = GPIOA[19]; assign Ld_o[4] = GPIOA[20]; assign Ld_o[5] = GPIOA[21]; assign Ld_o[6] = GPIOA[22]; assign LD_o = Ld_o[0]&Ld_o[1]&Ld_o[2]&Ld_o[3]&Ld_o[4]&Ld_o[5]&Ld_o[6]; assign wordCntRx[0] = spi0RxFifoCtrlRR[15:8]; assign wordCntRx[1] = spi1RxFifoCtrlRR[15:8]; assign wordCntRx[2] = spi2RxFifoCtrlRR[15:8]; assign wordCntRx[3] = spi3RxFifoCtrlRR[15:8]; assign wordCntRx[4] = spi4RxFifoCtrlRR[15:8]; assign wordCntRx[5] = spi5RxFifoCtrlRR[15:8]; assign wordCntRx[6] = spi6RxFifoCtrlRR[15:8]; assign wordCntTx[0] = spi0TxFifoCtrlRR[15:8]; assign wordCntTx[1] = spi1TxFifoCtrlRR[15:8]; assign wordCntTx[2] = spi2TxFifoCtrlRR[15:8]; assign wordCntTx[3] = spi3TxFifoCtrlRR[15:8]; assign wordCntTx[4] = spi4TxFifoCtrlRR[15:8]; assign wordCntTx[5] = spi5TxFifoCtrlRR[15:8]; assign wordCntTx[6] = spi6TxFifoCtrlRR[15:8]; assign chipSelFpga[0] = spi0CsCtrlRR[0]; assign chipSelFpga[1] = spi1CsCtrlRR[0]; assign chipSelFpga[2] = spi2CsCtrlRR[0]; assign chipSelFpga[3] = spi3CsCtrlRR[0]; assign chipSelFpga[4] = spi4CsCtrlRR[0]; assign chipSelFpga[5] = spi5CsCtrlRR[0]; assign chipSelFpga[6] = spi6CsCtrlRR[0]; assign chipSelFlash[0] = spi0CsCtrlRR[1]; assign chipSelFlash[1] = spi1CsCtrlRR[1]; assign chipSelFlash[2] = spi2CsCtrlRR[1]; assign chipSelFlash[3] = spi3CsCtrlRR[1]; assign chipSelFlash[4] = spi4CsCtrlRR[1]; assign chipSelFlash[5] = spi5CsCtrlRR[1]; assign chipSelFlash[6] = spi6CsCtrlRR[1]; assign ssMuxed[0] = (spiMode[0])? ssQ[0]:ssR[0]; assign ssMuxed[1] = (spiMode[1])? ssQ[1]:ssR[1]; assign ssMuxed[2] = (spiMode[2])? ssQ[2]:ssR[2]; assign ssMuxed[3] = (spiMode[3])? ssQ[3]:ssR[3]; assign ssMuxed[4] = (spiMode[4])? ssQ[4]:ssR[4]; assign ssMuxed[5] = (spiMode[5])? ssQ[5]:ssR[5]; assign ssMuxed[6] = (spiMode[6])? ssQ[6]:ssR[6]; assign SpiDir_o[0] = (spiMode[0])? 1'b1 : 1'b0 ; assign SpiDir_o[1] = (spiMode[1])? 1'b1 : 1'b0 ; assign SpiDir_o[2] = (spiMode[2])? 1'b1 : 1'b0 ; assign SpiDir_o[3] = (spiMode[3])? 1'b1 : 1'b0 ; assign SpiDir_o[4] = (spiMode[4])? 1'b1 : 1'b0 ; assign SpiDir_o[5] = (spiMode[5])? 1'b1 : 1'b0 ; assign SpiDir_o[6] = (spiMode[6])? 1'b1 : 1'b0 ; assign sckMuxed[0] = (spiMode[0])?sckQ[0]:sckR[0]; assign sckMuxed[1] = (spiMode[1])?sckQ[1]:sckR[1]; assign sckMuxed[2] = (spiMode[2])?sckQ[2]:sckR[2]; assign sckMuxed[3] = (spiMode[3])?sckQ[3]:sckR[3]; assign sckMuxed[4] = (spiMode[4])?sckQ[4]:sckR[4]; assign sckMuxed[5] = (spiMode[5])?sckQ[5]:sckR[5]; assign sckMuxed[6] = (spiMode[6])?sckQ[6]:sckR[6]; assign mosi0[0] = (spiMode[0])?mosi0Q[0]:mosi0R[0]; assign mosi0[1] = (spiMode[1])?mosi0Q[1]:mosi0R[1]; assign mosi0[2] = (spiMode[2])?mosi0Q[2]:mosi0R[2]; assign mosi0[3] = (spiMode[3])?mosi0Q[3]:mosi0R[3]; assign mosi0[4] = (spiMode[4])?mosi0Q[4]:mosi0R[4]; assign mosi0[5] = (spiMode[5])?mosi0Q[5]:mosi0R[5]; assign mosi0[6] = (spiMode[6])?mosi0Q[6]:mosi0R[6]; assign Mosi0_o[0] = mosi0[0]; assign Mosi0_o[1] = mosi0[1]; assign Mosi0_o[2] = mosi0[2]; assign Mosi0_o[3] = mosi0[3]; assign Mosi0_o[4] = mosi0[4]; assign Mosi0_o[5] = mosi0[5]; assign Mosi0_o[6] = mosi0[6]; assign valToTxFifoRead[0] = (spiMode[0])?valToTxQ[0]:valToTxR[0]; assign valToTxFifoRead[1] = (spiMode[1])?valToTxQ[1]:valToTxR[1]; assign valToTxFifoRead[2] = (spiMode[2])?valToTxQ[2]:valToTxR[2]; assign valToTxFifoRead[3] = (spiMode[3])?valToTxQ[3]:valToTxR[3]; assign valToTxFifoRead[4] = (spiMode[4])?valToTxQ[4]:valToTxR[4]; assign valToTxFifoRead[5] = (spiMode[5])?valToTxQ[5]:valToTxR[5]; assign valToTxFifoRead[6] = (spiMode[6])?valToTxQ[6]:valToTxR[6]; assign valToRxFifo[0] = valToRxR[0]; assign valToRxFifo[1] = valToRxR[1]; assign valToRxFifo[2] = valToRxR[2]; assign valToRxFifo[3] = valToRxR[3]; assign valToRxFifo[4] = valToRxR[4]; assign valToRxFifo[5] = valToRxR[5]; assign valToRxFifo[6] = valToRxR[6]; assign dataToRxFifo[0] = dataToRxFifoR[0]; assign dataToRxFifo[1] = dataToRxFifoR[1]; assign dataToRxFifo[2] = dataToRxFifoR[2]; assign dataToRxFifo[3] = dataToRxFifoR[3]; assign dataToRxFifo[4] = dataToRxFifoR[4]; assign dataToRxFifo[5] = dataToRxFifoR[5]; assign dataToRxFifo[6] = dataToRxFifoR[6]; assign spi0TxFifoCtrlReg = txFifoCtrlReg[0]; assign spi1TxFifoCtrlReg = txFifoCtrlReg[1]; assign spi2TxFifoCtrlReg = txFifoCtrlReg[2]; assign spi3TxFifoCtrlReg = txFifoCtrlReg[3]; assign spi4TxFifoCtrlReg = txFifoCtrlReg[4]; assign spi5TxFifoCtrlReg = txFifoCtrlReg[5]; assign spi6TxFifoCtrlReg = txFifoCtrlReg[6]; assign spi0RxFifoCtrlReg = rxFifoCtrlReg[0]; assign spi1RxFifoCtrlReg = rxFifoCtrlReg[1]; assign spi2RxFifoCtrlReg = rxFifoCtrlReg[2]; assign spi3RxFifoCtrlReg = rxFifoCtrlReg[3]; assign spi4RxFifoCtrlReg = rxFifoCtrlReg[4]; assign spi5RxFifoCtrlReg = rxFifoCtrlReg[5]; assign spi6RxFifoCtrlReg = rxFifoCtrlReg[6]; assign SmcData_io = (!SmcAre_i && !SmcAoe_i)?muxedData:16'bz; //================================================================================ // CODING //================================================================================ DataOutMux DataOutMuxer ( .Clk_i(gclk), .Addr_i(addrExt), .ToRegMapAddr_i(toRegMapAddr), .FifoRxRst_i(fifoRxRstRdPtr[0]), .DataFromRegMap_i(ansData), .SmcAre_i(SmcAre_i), .DataFromRxFifo1_i(dataFromRxFifo[0]), .DataFromRxFifo2_i(dataFromRxFifo[1]), .DataFromRxFifo3_i(dataFromRxFifo[2]), .DataFromRxFifo4_i(dataFromRxFifo[3]), .DataFromRxFifo5_i(dataFromRxFifo[4]), .DataFromRxFifo6_i(dataFromRxFifo[5]), .DataFromRxFifo7_i(dataFromRxFifo[6]), .AnsData_o (muxedData) ); BUFG BUFG_inst ( .O(gclk), // 1-bit output: Clock output .I(Clk123_i) // 1-bit input: Clock input ); DataMuxer DataMuxer ( .Clk_i(gclk), .Rst_i(initRst), .SmcVal_i(smcValComb), .SmcData_i(SmcData_io), .SmcAddr_i(addrExt), .ToRegMapVal_o(toRegMapVal), .ToRegMapData_o(toRegMapData), .ToRegMapAddr_o(toRegMapAddr), .ToFifoVal_o(toFifoVal), .ToFifoData_o(toFifoData) ); CDC #( .WIDTH(CmdRegWidth), .STAGES(STAGES) ) synchronizer( .ClkFast_i(gclk), .ClkSlow_i(spiClkBus), .Spi0Ctrl_i(spi0Ctrl), .Spi0CsCtrl_i(spi0CsCtrl), .Spi0CsDelay_i(spi0CsDelay), .Spi0TxFifoCtrl_i(spi0TxFifoCtrl), .Spi0RxFifoCtrl_i(spi0RxFifoCtrl), .Spi1Ctrl_i(spi1Ctrl), .Spi1CsCtrl_i(spi1CsCtrl), .Spi1CsDelay_i(spi1CsDelay), .Spi1TxFifoCtrl_i(spi1TxFifoCtrl), .Spi1RxFifoCtrl_i(spi1RxFifoCtrl), .Spi2Ctrl_i(spi2Ctrl), .Spi2CsCtrl_i(spi2CsCtrl), .Spi2CsDelay_i(spi2CsDelay), .Spi2TxFifoCtrl_i(spi2TxFifoCtrl), .Spi2RxFifoCtrl_i(spi2RxFifoCtrl), .Spi3Ctrl_i(spi3Ctrl), .Spi3CsCtrl_i(spi3CsCtrl), .Spi3CsDelay_i(spi3CsDelay), .Spi3TxFifoCtrl_i(spi3TxFifoCtrl), .Spi3RxFifoCtrl_i(spi3RxFifoCtrl), .Spi4Ctrl_i(spi4Ctrl), .Spi4CsCtrl_i(spi4CsCtrl), .Spi4CsDelay_i(spi4CsDelay), .Spi4TxFifoCtrl_i(spi4TxFifoCtrl), .Spi4RxFifoCtrl_i(spi4RxFifoCtrl), .Spi5Ctrl_i(spi5Ctrl), .Spi5CsCtrl_i(spi5CsCtrl), .Spi5CsDelay_i(spi5CsDelay), .Spi5TxFifoCtrl_i(spi5TxFifoCtrl), .Spi5RxFifoCtrl_i(spi5RxFifoCtrl), .Spi6Ctrl_i(spi6Ctrl), .Spi6CsCtrl_i(spi6CsCtrl), .Spi6CsDelay_i(spi6CsDelay), .Spi6TxFifoCtrl_i(spi6TxFifoCtrl), .Spi6RxFifoCtrl_i(spi6RxFifoCtrl), .Spi0Ctrl_o(spi0CtrlRR), .Spi0CsCtrl_o(spi0CsCtrlRR), .Spi0CsDelay_o(spi0CsDelayRR), .Spi0TxFifoCtrl_o(spi0TxFifoCtrlRR), .Spi0RxFifoCtrl_o(spi0RxFifoCtrlRR), .Spi1Ctrl_o(spi1CtrlRR), .Spi1CsCtrl_o(spi1CsCtrlRR), .Spi1CsDelay_o(spi1CsDelayRR), .Spi1TxFifoCtrl_o(spi1TxFifoCtrlRR), .Spi1RxFifoCtrl_o(spi1RxFifoCtrlRR), .Spi2Ctrl_o(spi2CtrlRR), .Spi2CsCtrl_o(spi2CsCtrlRR), .Spi2CsDelay_o(spi2CsDelayRR), .Spi2TxFifoCtrl_o(spi2TxFifoCtrlRR), .Spi2RxFifoCtrl_o(spi2RxFifoCtrlRR), .Spi3Ctrl_o(spi3CtrlRR), .Spi3CsCtrl_o(spi3CsCtrlRR), .Spi3CsDelay_o(spi3CsDelayRR), .Spi3TxFifoCtrl_o(spi3TxFifoCtrlRR), .Spi3RxFifoCtrl_o(spi3RxFifoCtrlRR), .Spi4Ctrl_o(spi4CtrlRR), .Spi4CsCtrl_o(spi4CsCtrlRR), .Spi4CsDelay_o(spi4CsDelayRR), .Spi4TxFifoCtrl_o(spi4TxFifoCtrlRR), .Spi4RxFifoCtrl_o(spi4RxFifoCtrlRR), .Spi5Ctrl_o(spi5CtrlRR), .Spi5CsCtrl_o(spi5CsCtrlRR), .Spi5CsDelay_o(spi5CsDelayRR), .Spi5TxFifoCtrl_o(spi5TxFifoCtrlRR), .Spi5RxFifoCtrl_o(spi5RxFifoCtrlRR), .Spi6Ctrl_o(spi6CtrlRR), .Spi6CsCtrl_o(spi6CsCtrlRR), .Spi6CsDelay_o(spi6CsDelayRR), .Spi6TxFifoCtrl_o(spi6TxFifoCtrlRR), .Spi6RxFifoCtrl_o(spi6RxFifoCtrlRR) ); RegMap #( .CmdRegWidth(32), .AddrRegWidth(12) ) RegMap_inst ( .Clk_i(gclk), .Rst_i(initRst), .Data_i(toRegMapData), .Addr_i(toRegMapAddr), .Val_i(toRegMapVal), .SmcBe_i(SmcBe_i), .TxFifoCtrlReg0_i(spi0TxFifoCtrlReg), .TxFifoCtrlReg1_i(spi1TxFifoCtrlReg), .TxFifoCtrlReg2_i(spi2TxFifoCtrlReg), .TxFifoCtrlReg3_i(spi3TxFifoCtrlReg), .TxFifoCtrlReg4_i(spi4TxFifoCtrlReg), .TxFifoCtrlReg5_i(spi5TxFifoCtrlReg), .TxFifoCtrlReg6_i(spi6TxFifoCtrlReg), .RxFifoCtrlReg0_i(spi0RxFifoCtrlReg), .RxFifoCtrlReg1_i(spi1RxFifoCtrlReg), .RxFifoCtrlReg2_i(spi2RxFifoCtrlReg), .RxFifoCtrlReg3_i(spi3RxFifoCtrlReg), .RxFifoCtrlReg4_i(spi4RxFifoCtrlReg), .RxFifoCtrlReg5_i(spi5RxFifoCtrlReg), .RxFifoCtrlReg6_i(spi6RxFifoCtrlReg), //Spi0 .Spi0CtrlReg_o(spi0Ctrl), .Spi0ClkReg_o(spi0Clk), .Spi0CsDelayReg_o(spi0CsDelay), .Spi0CsCtrlReg_o(spi0CsCtrl), .Spi0TxFifoCtrlReg_o(spi0TxFifoCtrl), .Spi0RxFifoCtrlReg_o(spi0RxFifoCtrl), //Spi1 .Spi1CtrlReg_o(spi1Ctrl), .Spi1ClkReg_o(spi1Clk), .Spi1CsDelayReg_o(spi1CsDelay), .Spi1CsCtrlReg_o(spi1CsCtrl), .Spi1TxFifoCtrlReg_o(spi1TxFifoCtrl), .Spi1RxFifoCtrlReg_o(spi1RxFifoCtrl), //Spi2 .Spi2CtrlReg_o(spi2Ctrl), .Spi2ClkReg_o(spi2Clk), .Spi2CsDelayReg_o(spi2CsDelay), .Spi2CsCtrlReg_o(spi2CsCtrl), .Spi2TxFifoCtrlReg_o(spi2TxFifoCtrl), .Spi2RxFifoCtrlReg_o(spi2RxFifoCtrl), //Spi3 .Spi3CtrlReg_o(spi3Ctrl), .Spi3ClkReg_o(spi3Clk), .Spi3CsDelayReg_o(spi3CsDelay), .Spi3CsCtrlReg_o(spi3CsCtrl), .Spi3TxFifoCtrlReg_o(spi3TxFifoCtrl), .Spi3RxFifoCtrlReg_o(spi3RxFifoCtrl), //Spi4 .Spi4CtrlReg_o(spi4Ctrl), .Spi4ClkReg_o(spi4Clk), .Spi4CsDelayReg_o(spi4CsDelay), .Spi4CsCtrlReg_o(spi4CsCtrl), .Spi4TxFifoCtrlReg_o(spi4TxFifoCtrl), .Spi4RxFifoCtrlReg_o(spi4RxFifoCtrl), //Spi5 .Spi5CtrlReg_o(spi5Ctrl), .Spi5ClkReg_o(spi5Clk), .Spi5CsDelayReg_o(spi5CsDelay), .Spi5CsCtrlReg_o(spi5CsCtrl), .Spi5TxFifoCtrlReg_o(spi5TxFifoCtrl), .Spi5RxFifoCtrlReg_o(spi5RxFifoCtrl), //Spi6 .Spi6CtrlReg_o(spi6Ctrl), .Spi6ClkReg_o(spi6Clk), .Spi6CsDelayReg_o(spi6CsDelay), .Spi6CsCtrlReg_o(spi6CsCtrl), .Spi6TxFifoCtrlReg_o(spi6TxFifoCtrl), .Spi6RxFifoCtrlReg_o(spi6RxFifoCtrl), .SpiTxRxEnReg_o(spiTxRxEn), .GPIOAReg_o(GPIOA), .Led_o(Led_o), .AnsDataReg_o(ansData) ); MmcmWrapper #( .SpiNum(SpiNum) ) MainMmcm ( .Clk_i(gclk), .Rst_i(initRst), .Rst80_i(rst80), .BaudRate0_i(baudRate[0]), .BaudRate1_i(baudRate[1]), .BaudRate2_i(baudRate[2]), .BaudRate3_i(baudRate[3]), .BaudRate4_i(baudRate[4]), .BaudRate5_i(baudRate[5]), .BaudRate6_i(baudRate[6]), .Clk80_o(clk80), .SpiClk_o(spiClkBus) ); genvar i; generate for (i = 0; i < SpiNum; i = i + 1) begin: SpiGen InitRst InitRst_inst ( .clk_i(spiClkBus[i]), .signal_o(initRstGen[i]) ); Sync1bit#( .WIDTH(1), .STAGES(STAGES) ) Sync1bit_inst( .ClkFast_i(gclk), .ClkSlow_i(spiClkBus[i]), .TxEn_i(txEn[i]), .RstReg_i(GPIOA[i]), .TxEn_o(spiTxEnSync[i]), .RstReg_o(GPIOASync[i]) ); DataFifoWrapper #( .STAGES(STAGES) )DataFifoWrapper ( .WrClk_i(gclk), .RdClk_i(spiClkBus[i]), .FifoRxRst_i(fifoRxRst[i]), .FifoTxRst_i(fifoTxRst[i]), .FifoRxRstRdPtr_i(fifoRxRstRdPtr[i]), .FifoTxRstWrPtr_i(fifoTxRstWrPtr[i]), .SmcAre_i(SmcAre_i), .SmcAwe_i(SmcAwe_i), .SmcAddr_i(addrExt), .TxFifoWrdCnt_i(wordCntTx[i]), .RxFifoWrdCnt_i(wordCntRx[i]), .ToFifoVal_i(toFifoVal[i]), .ToFifoRxData_i(dataToRxFifo[i]), .ToFifoRxWriteVal_i(valToRxFifo[i]), .ToFifoTxReadVal_i(valToTxFifoRead[i]), .ToFifoData_i(toFifoData[32*i+:32]), .TxFifoCtrlReg_o(txFifoCtrlReg[i]), .RxFifoCtrlReg_o(rxFifoCtrlReg[i]), .ToSpiVal_o(toSpiVal[i]), .DataFromRxFifo_o(dataFromRxFifo[i]), .ToSpiData_o(toSpiData[i]) ); SPIm SPIm_inst ( .Clk_i(spiClkBus[i]), .Start_i(spiTxEnSync[i]), .Rst_i(initRstGen[i]| spiMode[i]), .SpiData_i(toSpiData[i]), .Sck_o(sckR[i]), .Ss_o(ssR[i]), .Mosi0_o(mosi0R[i]), .WidthSel_i(widthSel[i]), .PulsePol_i(clockPol[i]), .ClockPhase_i(clockPhase[i]), .EndianSel_i(endianSel[i]), .Lag_i(lag[i]), .Lead_i(leadx[i]), .Stop_i(stopDelay[i]), .SelSt_i(selSt[i]), .Val_o(valToTxR[i]) ); SPIs SPIs_inst ( .Clk_i(spiClkBus[i]), .Rst_i(initRstGen[i]|SpiRst_o[i]| spiMode[i]), .Sck_i(sckR[i]), .Ss_i(ssR[i]), .Mosi0_i(Mosi1_io[i]), .WidthSel_i(widthSel[i]), .SelSt_i(selSt[i]), .DataToRxFifo_o(dataToRxFifoR[i]), .Val_o(valToRxR[i]) ); QuadSPIm QuadSPIm_inst ( .Clk_i(spiClkBus[i]), .Start_i(spiTxEnSync[i]), .Rst_i(initRstGen[i]| !spiMode[i]), .SpiDataVal_i(toSpiVal), .SpiData_i(toSpiData[i]), .Sck_o(sckQ[i]), .Ss_o(ssQ[i]), .Mosi0_i(mosi0Q[i]), .Mosi1_i(mosi1[i]), .Mosi2_i(mosi2[i]), .Mosi3_i(mosi3[i]), .WidthSel_i(widthSel[i]), .PulsePol_i(clockPol[i]), .ClockPhase_i(clockPhase[i]), .EndianSel_i(endianSel[i]), .Lag_i(lag[i]), .Lead_i(leadx[i]), .Stop_i(stopDelay[i]), .SelSt_i(selSt[i]), .Val_o(valToTxQ[i]) ); end endgenerate InitRst InitRst_inst ( .clk_i(gclk), .signal_o(initRst) ); InitRst Rst80_inst ( .clk_i(clk80), .signal_o(rst80) ); endmodule