module RegMap #( parameter CmdRegWidth = 32, parameter AddrRegWidth = 12 ) ( input [CmdRegWidth/2-1:0] Data_i, input [AddrRegWidth-1:0] Addr_i, input Val_i, input Clk_i, input Rst_i, input [1:0] SmcBe_i, output [CmdRegWidth/2-1:0] Spi0CtrlReg_o, output [CmdRegWidth/2-1:0] Spi0ClkReg_o, output [CmdRegWidth/2-1:0] Spi0CsDelayReg_o, output [CmdRegWidth/2-1:0] Spi0CsCtrlReg_o, output [CmdRegWidth/2-1:0] Spi0TxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi0RxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi0TxFifoReg_o, output [CmdRegWidth/2-1:0] Spi0RxFifoReg_o, output [CmdRegWidth/2-1:0] Spi1CtrlReg_o, output [CmdRegWidth/2-1:0] Spi1ClkReg_o, output [CmdRegWidth/2-1:0] Spi1CsDelayReg_o, output [CmdRegWidth/2-1:0] Spi1CsCtrlReg_o, output [CmdRegWidth/2-1:0] Spi1TxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi1RxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi1TxFifoReg_o, output [CmdRegWidth/2-1:0] Spi1RxFifoReg_o, output [CmdRegWidth/2-1:0] Spi2CtrlReg_o, output [CmdRegWidth/2-1:0] Spi2ClkReg_o, output [CmdRegWidth/2-1:0] Spi2CsDelayReg_o, output [CmdRegWidth/2-1:0] Spi2CsCtrlReg_o, output [CmdRegWidth/2-1:0] Spi2TxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi2RxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi2TxFifoReg_o, output [CmdRegWidth/2-1:0] Spi2RxFifoReg_o, output [CmdRegWidth/2-1:0] Spi3CtrlReg_o, output [CmdRegWidth/2-1:0] Spi3ClkReg_o, output [CmdRegWidth/2-1:0] Spi3CsDelayReg_o, output [CmdRegWidth/2-1:0] Spi3CsCtrlReg_o, output [CmdRegWidth/2-1:0] Spi3TxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi3RxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi3TxFifoReg_o, output [CmdRegWidth/2-1:0] Spi3RxFifoReg_o, output [CmdRegWidth/2-1:0] Spi4CtrlReg_o, output [CmdRegWidth/2-1:0] Spi4ClkReg_o, output [CmdRegWidth/2-1:0] Spi4CsDelayReg_o, output [CmdRegWidth/2-1:0] Spi4CsCtrlReg_o, output [CmdRegWidth/2-1:0] Spi4TxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi4RxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi4TxFifoReg_o, output [CmdRegWidth/2-1:0] Spi4RxFifoReg_o, output [CmdRegWidth/2-1:0] Spi5CtrlReg_o, output [CmdRegWidth/2-1:0] Spi5ClkReg_o, output [CmdRegWidth/2-1:0] Spi5CsDelayReg_o, output [CmdRegWidth/2-1:0] Spi5CsCtrlReg_o, output [CmdRegWidth/2-1:0] Spi5TxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi5RxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi5TxFifoReg_o, output [CmdRegWidth/2-1:0] Spi5RxFifoReg_o, output [CmdRegWidth/2-1:0] Spi6CtrlReg_o, output [CmdRegWidth/2-1:0] Spi6ClkReg_o, output [CmdRegWidth/2-1:0] Spi6CsDelayReg_o, output [CmdRegWidth/2-1:0] Spi6CsCtrlReg_o, output [CmdRegWidth/2-1:0] Spi6TxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi6RxFifoCtrlReg_o, output [CmdRegWidth/2-1:0] Spi6TxFifoReg_o, output [CmdRegWidth/2-1:0] Spi6RxFifoReg_o, output [CmdRegWidth/2-1:0] SpiTxRxEnReg_o, output [CmdRegWidth-1:0] GPIOAReg_o, output [CmdRegWidth/2-1:0] AnsDataReg_o, output Led_o ); //================================================================================ // REG/WIRE //================================================================================ reg [CmdRegWidth/2-1:0] Spi0CtrlReg; reg [CmdRegWidth/2-1:0] Spi0ClkReg; reg [CmdRegWidth/2-1:0] Spi0CsDelayReg; reg [CmdRegWidth/2-1:0] Spi0CsCtrlReg; reg [CmdRegWidth/2-1:0] Spi0TxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi0RxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi0TxFifoReg; reg [CmdRegWidth/2-1:0] Spi0RxFifoReg; reg [CmdRegWidth/2-1:0] Spi1CtrlReg; reg [CmdRegWidth/2-1:0] Spi1ClkReg; reg [CmdRegWidth/2-1:0] Spi1CsDelayReg; reg [CmdRegWidth/2-1:0] Spi1CsCtrlReg; reg [CmdRegWidth/2-1:0] Spi1TxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi1RxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi1TxFifoReg; reg [CmdRegWidth/2-1:0] Spi1RxFifoReg; reg [CmdRegWidth/2-1:0] Spi2CtrlReg; reg [CmdRegWidth/2-1:0] Spi2ClkReg; reg [CmdRegWidth/2-1:0] Spi2CsDelayReg; reg [CmdRegWidth/2-1:0] Spi2CsCtrlReg; reg [CmdRegWidth/2-1:0] Spi2TxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi2RxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi2TxFifoReg; reg [CmdRegWidth/2-1:0] Spi2RxFifoReg; reg [CmdRegWidth/2-1:0] Spi3CtrlReg; reg [CmdRegWidth/2-1:0] Spi3ClkReg; reg [CmdRegWidth/2-1:0] Spi3CsDelayReg; reg [CmdRegWidth/2-1:0] Spi3CsCtrlReg; reg [CmdRegWidth/2-1:0] Spi3TxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi3RxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi3TxFifoReg; reg [CmdRegWidth/2-1:0] Spi3RxFifoReg; reg [CmdRegWidth/2-1:0] Spi4CtrlReg; reg [CmdRegWidth/2-1:0] Spi4ClkReg; reg [CmdRegWidth/2-1:0] Spi4CsDelayReg; reg [CmdRegWidth/2-1:0] Spi4CsCtrlReg; reg [CmdRegWidth/2-1:0] Spi4TxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi4RxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi4TxFifoReg; reg [CmdRegWidth/2-1:0] Spi4RxFifoReg; reg [CmdRegWidth/2-1:0] Spi5CtrlReg; reg [CmdRegWidth/2-1:0] Spi5ClkReg; reg [CmdRegWidth/2-1:0] Spi5CsDelayReg; reg [CmdRegWidth/2-1:0] Spi5CsCtrlReg; reg [CmdRegWidth/2-1:0] Spi5TxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi5RxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi5TxFifoReg; reg [CmdRegWidth/2-1:0] Spi5RxFifoReg; reg [CmdRegWidth/2-1:0] Spi6CtrlReg; reg [CmdRegWidth/2-1:0] Spi6ClkReg; reg [CmdRegWidth/2-1:0] Spi6CsDelayReg; reg [CmdRegWidth/2-1:0] Spi6CsCtrlReg; reg [CmdRegWidth/2-1:0] Spi6TxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi6RxFifoCtrlReg; reg [CmdRegWidth/2-1:0] Spi6TxFifoReg; reg [CmdRegWidth/2-1:0] Spi6RxFifoReg; (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] SpiTxRxEnReg; reg [CmdRegWidth/2-1:0] GPIOAReg; reg [CmdRegWidth/2-1:0] GPIOARegS; (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] ansReg; (* dont_touch = "yes" *)reg [CmdRegWidth/2-1:0] LedReg; //================================================================================ // ASSIGNMENTS //================================================================================ assign Spi0CtrlReg_o = Spi0CtrlReg; assign Spi0ClkReg_o = Spi0ClkReg; assign Spi0CsDelayReg_o = Spi0CsDelayReg; assign Spi0CsCtrlReg_o = Spi0CsCtrlReg; assign Spi0TxFifoCtrlReg_o = Spi0TxFifoCtrlReg; assign Spi0RxFifoCtrlReg_o = Spi0RxFifoCtrlReg; assign Spi0TxFifoReg_o = Spi0TxFifoReg; assign Spi0RxFifoReg_o = Spi0RxFifoReg; assign Spi1CtrlReg_o = Spi1CtrlReg; assign Spi1ClkReg_o = Spi1ClkReg; assign Spi1CsDelayReg_o = Spi1CsDelayReg; assign Spi1CsCtrlReg_o = Spi1CsCtrlReg; assign Spi1TxFifoCtrlReg_o = Spi1TxFifoCtrlReg; assign Spi1RxFifoCtrlReg_o = Spi1RxFifoCtrlReg; assign Spi1TxFifoReg_o = Spi1TxFifoReg; assign Spi1RxFifoReg_o = Spi1RxFifoReg; assign Spi2CtrlReg_o = Spi2CtrlReg; assign Spi2ClkReg_o = Spi2ClkReg; assign Spi2CsDelayReg_o = Spi2CsDelayReg; assign Spi2CsCtrlReg_o = Spi2CsCtrlReg; assign Spi2TxFifoCtrlReg_o = Spi2TxFifoCtrlReg; assign Spi2RxFifoCtrlReg_o = Spi2RxFifoCtrlReg; assign Spi2TxFifoReg_o = Spi2TxFifoReg; assign Spi2RxFifoReg_o = Spi2RxFifoReg; assign Spi3CtrlReg_o = Spi3CtrlReg; assign Spi3ClkReg_o = Spi3ClkReg; assign Spi3CsDelayReg_o = Spi3CsDelayReg; assign Spi3CsCtrlReg_o = Spi3CsCtrlReg; assign Spi3TxFifoCtrlReg_o = Spi3TxFifoCtrlReg; assign Spi3RxFifoCtrlReg_o = Spi3RxFifoCtrlReg; assign Spi3TxFifoReg_o = Spi3TxFifoReg; assign Spi3RxFifoReg_o = Spi3RxFifoReg; assign Spi4CtrlReg_o = Spi4CtrlReg; assign Spi4ClkReg_o = Spi4ClkReg; assign Spi4CsDelayReg_o = Spi4CsDelayReg; assign Spi4CsCtrlReg_o = Spi4CsCtrlReg; assign Spi4TxFifoCtrlReg_o = Spi4TxFifoCtrlReg; assign Spi4RxFifoCtrlReg_o = Spi4RxFifoCtrlReg; assign Spi4TxFifoReg_o = Spi4TxFifoReg; assign Spi4RxFifoReg_o = Spi4RxFifoReg; assign Spi5CtrlReg_o = Spi5CtrlReg; assign Spi5ClkReg_o = Spi5ClkReg; assign Spi5CsDelayReg_o = Spi5CsDelayReg; assign Spi5CsCtrlReg_o = Spi5CsCtrlReg; assign Spi5TxFifoCtrlReg_o = Spi5TxFifoCtrlReg; assign Spi5RxFifoCtrlReg_o = Spi5RxFifoCtrlReg; assign Spi5TxFifoReg_o = Spi5TxFifoReg; assign Spi5RxFifoReg_o = Spi5RxFifoReg; assign Spi6CtrlReg_o = Spi6CtrlReg; assign Spi6ClkReg_o = Spi6ClkReg; assign Spi6CsDelayReg_o = Spi6CsDelayReg; assign Spi6CsCtrlReg_o = Spi6CsCtrlReg; assign Spi6TxFifoCtrlReg_o = Spi6TxFifoCtrlReg; assign Spi6RxFifoCtrlReg_o = Spi6RxFifoCtrlReg; assign Spi6TxFifoReg_o = Spi6TxFifoReg; assign Spi6RxFifoReg_o = Spi6RxFifoReg; assign SpiTxRxEnReg_o = SpiTxRxEnReg; assign GPIOAReg_o = {GPIOARegS, GPIOAReg}; assign AnsDataReg_o = ansReg; assign Led_o = LedReg[0]; //================================================================================ // LOCALPARAMS //================================================================================ localparam Spi0CtrlAddr = 12'h00; localparam Spi0ClkAddr = 12'h04; localparam Spi0CsDelayAddr = 12'h08; localparam Spi0CsCtrlAddr = 12'h0c; localparam Spi0TxFifoCtrlAddr = 12'h10; localparam Spi0RxFifoCtrlAddr = 12'h14; localparam Spi0TxFifo = 12'h18; localparam Spi0RxFifo = 12'h1c; localparam Spi1CtrlAddr = 12'h50; localparam Spi1ClkAddr = 12'h54; localparam Spi1CsDelayAddr = 12'h58; localparam Spi1CsCtrlAddr = 12'h5c; localparam Spi1TxFifoCtrlAddr = 12'h60; localparam Spi1RxFifoCtrlAddr = 12'h64; localparam Spi1TxFifo = 12'h68; localparam Spi1RxFifo = 12'h6c; localparam Spi2CtrlAddr = 12'hF0; localparam Spi2ClkAddr = 12'hF4; localparam Spi2CsDelayAddr = 12'hF8; localparam Spi2CsCtrlAddr = 12'hFc; localparam Spi2TxFifoCtrlAddr = 12'h100; localparam Spi2RxFifoCtrlAddr = 12'h104; localparam Spi2TxFifo = 12'h108; localparam Spi2RxFifo = 12'h10c; localparam Spi3CtrlAddr = 12'h140; localparam Spi3ClkAddr = 12'h144; localparam Spi3CsDelayAddr = 12'h148; localparam Spi3CsCtrlAddr = 12'h14c; localparam Spi3TxFifoCtrlAddr = 12'h150; localparam Spi3RxFifoCtrlAddr = 12'h154; localparam Spi3TxFifo = 12'h158; localparam Spi3RxFifo = 12'h15c; localparam Spi4CtrlAddr = 12'h190; localparam Spi4ClkAddr = 12'h194; localparam Spi4CsDelayAddr = 12'h198; localparam Spi4CsCtrlAddr = 12'h19c; localparam Spi4TxFifoCtrlAddr = 12'h1a0; localparam Spi4RxFifoCtrlAddr = 12'h1a4; localparam Spi4TxFifo = 12'h1a8; localparam Spi4RxFifo = 12'h1ac; localparam Spi5CtrlAddr = 12'h1e0; localparam Spi5ClkAddr = 12'h1e4; localparam Spi5CsDelayAddr = 12'h1e8; localparam Spi5CsCtrlAddr = 12'h1ec; localparam Spi5TxFifoCtrlAddr = 12'h1f0; localparam Spi5RxFifoCtrlAddr = 12'h1f4; localparam Spi5TxFifo = 12'h1f8; localparam Spi5RxFifo = 12'h1fc; localparam Spi6CtrlAddr = 12'h230; localparam Spi6ClkAddr = 12'h234; localparam Spi6CsDelayAddr = 12'h238; localparam Spi6CsCtrlAddr = 12'h23c; localparam Spi6TxFifoCtrlAddr = 12'h240; localparam Spi6RxFifoCtrlAddr = 12'h244; localparam Spi6TxFifo = 12'h248; localparam Spi6RxFifo = 12'h24c; localparam SpiTxRxEn = 12'hF00; localparam GPIOCtrlAddr = 12'hFF0; localparam GPIOCtrlAddrS = 12'hFF2; localparam Debug0Addr = 12'hFF8; localparam Debug1Addr = 12'hFFC; //================================================================================ always @(posedge Clk_i) begin if (Rst_i) begin Spi0ClkReg <= 0; Spi0CtrlReg <= 0; Spi0CsDelayReg <= 0; Spi0CsCtrlReg <= 0; Spi0TxFifoCtrlReg <= 0; Spi0RxFifoCtrlReg <= 0; Spi0TxFifoReg <= 0; Spi0RxFifoReg <= 0; Spi1ClkReg <= 0; Spi1CtrlReg <= 0; Spi1CsDelayReg <= 0; Spi1CsCtrlReg <= 0; Spi1TxFifoCtrlReg <= 0; Spi1RxFifoCtrlReg <= 0; Spi1TxFifoReg <= 0; Spi1RxFifoReg <= 0; Spi2ClkReg <= 0; Spi2CtrlReg <= 0; Spi2CsDelayReg <= 0; Spi2CsCtrlReg <= 0; Spi2TxFifoCtrlReg <= 0; Spi2RxFifoCtrlReg <= 0; Spi2TxFifoReg <= 0; Spi2RxFifoReg <= 0; Spi3ClkReg <= 0; Spi3CtrlReg <= 0; Spi3CsDelayReg <= 0; Spi3CsCtrlReg <= 0; Spi3TxFifoCtrlReg <= 0; Spi3RxFifoCtrlReg <= 0; Spi3TxFifoReg <= 0; Spi3RxFifoReg <= 0; Spi4ClkReg <= 0; Spi4CtrlReg <= 0; Spi4CsDelayReg <= 0; Spi4CsCtrlReg <= 0; Spi4TxFifoCtrlReg <= 0; Spi4RxFifoCtrlReg <= 0; Spi4TxFifoReg <= 0; Spi4RxFifoReg <= 0; Spi5ClkReg <= 0; Spi5CtrlReg <= 0; Spi5CsDelayReg <= 0; Spi5CsCtrlReg <= 0; Spi5TxFifoCtrlReg <= 0; Spi5RxFifoCtrlReg <= 0; Spi5TxFifoReg <= 0; Spi5RxFifoReg <= 0; Spi6ClkReg <= 0; Spi6CtrlReg <= 0; Spi6CsDelayReg <= 0; Spi6CsCtrlReg <= 0; Spi6TxFifoCtrlReg <= 0; Spi6RxFifoCtrlReg <= 0; Spi6TxFifoReg <= 0; Spi6RxFifoReg <= 0; SpiTxRxEnReg <= 0; GPIOAReg <= 0; GPIOARegS <= 0; LedReg <= 0; end else begin if (Val_i) begin case (SmcBe_i) 0 : begin case (Addr_i) Spi0CtrlAddr : begin Spi0CtrlReg <= Data_i; end Spi0ClkAddr : begin Spi0ClkReg <= Data_i; end Spi0CsDelayAddr : begin Spi0CsDelayReg <= Data_i; end Spi0CsCtrlAddr : begin Spi0CsCtrlReg <= Data_i; end Spi0TxFifoCtrlAddr : begin Spi0TxFifoCtrlReg <= Data_i; end Spi0RxFifoCtrlAddr : begin Spi0RxFifoCtrlReg <= Data_i; end Spi0TxFifo : begin Spi0TxFifoReg <= Data_i; end Spi0RxFifo : begin Spi0RxFifoReg <= Data_i; end Spi1CtrlAddr : begin Spi1CtrlReg <= Data_i; end Spi1ClkAddr : begin Spi1ClkReg <= Data_i; end Spi1CsDelayAddr : begin Spi1CsDelayReg <= Data_i; end Spi1CsCtrlAddr : begin Spi1CsCtrlReg <= Data_i; end Spi1TxFifoCtrlAddr : begin Spi1TxFifoCtrlReg <= Data_i; end Spi1RxFifoCtrlAddr : begin Spi1RxFifoCtrlReg <= Data_i; end Spi1TxFifo : begin Spi1TxFifoReg <= Data_i; end Spi1RxFifo : begin Spi1RxFifoReg <= Data_i; end Spi2CtrlAddr : begin Spi2CtrlReg <= Data_i; end Spi2ClkAddr : begin Spi2ClkReg <= Data_i; end Spi2CsDelayAddr : begin Spi2CsDelayReg <= Data_i; end Spi2CsCtrlAddr : begin Spi2CsCtrlReg <= Data_i; end Spi2TxFifoCtrlAddr : begin Spi2TxFifoCtrlReg <= Data_i; end Spi2RxFifoCtrlAddr : begin Spi2RxFifoCtrlReg <= Data_i; end Spi2TxFifo : begin Spi2TxFifoReg <= Data_i; end Spi2RxFifo : begin Spi2RxFifoReg <= Data_i; end Spi3CtrlAddr : begin Spi3CtrlReg <= Data_i; end Spi3ClkAddr : begin Spi3ClkReg <= Data_i; end Spi3CsDelayAddr : begin Spi3CsDelayReg <= Data_i; end Spi3CsCtrlAddr : begin Spi3CsCtrlReg <= Data_i; end Spi3TxFifoCtrlAddr : begin Spi3TxFifoCtrlReg <= Data_i; end Spi3RxFifoCtrlAddr : begin Spi3RxFifoCtrlReg <= Data_i; end Spi3TxFifo : begin Spi3TxFifoReg <= Data_i; end Spi3RxFifo : begin Spi3RxFifoReg <= Data_i; end Spi4CtrlAddr : begin Spi4CtrlReg <= Data_i; end Spi4ClkAddr : begin Spi4ClkReg <= Data_i; end Spi4CsDelayAddr : begin Spi4CsDelayReg <= Data_i; end Spi4CsCtrlAddr : begin Spi4CsCtrlReg <= Data_i; end Spi4TxFifoCtrlAddr : begin Spi4TxFifoCtrlReg <= Data_i; end Spi4RxFifoCtrlAddr : begin Spi4RxFifoCtrlReg <= Data_i; end Spi4TxFifo : begin Spi4TxFifoReg <= Data_i; end Spi4RxFifo : begin Spi4RxFifoReg <= Data_i; end Spi5CtrlAddr : begin Spi5CtrlReg <= Data_i; end Spi5ClkAddr : begin Spi5ClkReg <= Data_i; end Spi5CsDelayAddr : begin Spi5CsDelayReg <= Data_i; end Spi5CsCtrlAddr : begin Spi5CsCtrlReg <= Data_i; end Spi5TxFifoCtrlAddr : begin Spi5TxFifoCtrlReg <= Data_i; end Spi5RxFifoCtrlAddr : begin Spi5RxFifoCtrlReg <= Data_i; end Spi5TxFifo : begin Spi5TxFifoReg <= Data_i; end Spi5RxFifo : begin Spi5RxFifoReg <= Data_i; end Spi6CtrlAddr : begin Spi6CtrlReg <= Data_i; end Spi6ClkAddr : begin Spi6ClkReg <= Data_i; end Spi6CsDelayAddr : begin Spi6CsDelayReg <= Data_i; end Spi6CsCtrlAddr : begin Spi6CsCtrlReg <= Data_i; end Spi6TxFifoCtrlAddr : begin Spi6TxFifoCtrlReg <= Data_i; end Spi6RxFifoCtrlAddr : begin Spi6RxFifoCtrlReg <= Data_i; end Spi6TxFifo : begin Spi6TxFifoReg <= Data_i; end Spi6RxFifo : begin Spi6RxFifoReg <= Data_i; end SpiTxRxEn : begin SpiTxRxEnReg <= Data_i; end GPIOCtrlAddr : begin GPIOAReg <= Data_i; end GPIOCtrlAddrS : begin GPIOARegS <= Data_i; end Debug0Addr : begin LedReg <= Data_i; end endcase end 1 : begin case (Addr_i) Spi0CtrlAddr : begin Spi0CtrlReg[15:8] <= Data_i[15:8]; end Spi0ClkAddr : begin Spi0ClkReg[15:8] <= Data_i[15:8]; end Spi0CsDelayAddr : begin Spi0CsDelayReg[15:8] <= Data_i[15:8]; end Spi0CsCtrlAddr : begin Spi0CsCtrlReg[15:8] <= Data_i[15:8]; end Spi0TxFifoCtrlAddr : begin Spi0TxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi0RxFifoCtrlAddr : begin Spi0RxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi0TxFifo : begin Spi0TxFifoReg[15:8] <= Data_i[15:8]; end Spi0RxFifo : begin Spi0RxFifoReg[15:8] <= Data_i[15:8]; end Spi1CtrlAddr : begin Spi1CtrlReg[15:8] <= Data_i[15:8]; end Spi1ClkAddr : begin Spi1ClkReg[15:8] <= Data_i[15:8]; end Spi1CsDelayAddr : begin Spi1CsDelayReg[15:8] <= Data_i[15:8]; end Spi1CsCtrlAddr : begin Spi1CsCtrlReg[15:8] <= Data_i[15:8]; end Spi1TxFifoCtrlAddr : begin Spi1TxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi1RxFifoCtrlAddr : begin Spi1RxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi1TxFifo : begin Spi1TxFifoReg[15:8] <= Data_i[15:8]; end Spi1RxFifo : begin Spi1RxFifoReg[15:8] <= Data_i[15:8]; end Spi2CtrlAddr : begin Spi2CtrlReg[15:8] <= Data_i[15:8]; end Spi2ClkAddr : begin Spi2ClkReg[15:8] <= Data_i[15:8]; end Spi2CsDelayAddr : begin Spi2CsDelayReg[15:8] <= Data_i[15:8]; end Spi2CsCtrlAddr : begin Spi2CsCtrlReg[15:8] <= Data_i[15:8]; end Spi2TxFifoCtrlAddr : begin Spi2TxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi2RxFifoCtrlAddr : begin Spi2RxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi2TxFifo : begin Spi2TxFifoReg[15:8] <= Data_i[15:8]; end Spi2RxFifo : begin Spi2RxFifoReg[15:8] <= Data_i[15:8]; end Spi3CtrlAddr : begin Spi3CtrlReg[15:8] <= Data_i[15:8]; end Spi3ClkAddr : begin Spi3ClkReg[15:8] <= Data_i[15:8]; end Spi3CsDelayAddr : begin Spi3CsDelayReg[15:8] <= Data_i[15:8]; end Spi3CsCtrlAddr : begin Spi3CsCtrlReg[15:8] <= Data_i[15:8]; end Spi3TxFifoCtrlAddr : begin Spi3TxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi3RxFifoCtrlAddr : begin Spi3RxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi3TxFifo : begin Spi3TxFifoReg[15:8] <= Data_i[15:8]; end Spi3RxFifo : begin Spi3RxFifoReg[15:8] <= Data_i[15:8]; end Spi4CtrlAddr : begin Spi4CtrlReg[15:8] <= Data_i[15:8]; end Spi4ClkAddr : begin Spi4ClkReg[15:8] <= Data_i[15:8]; end Spi4CsDelayAddr : begin Spi4CsDelayReg[15:8] <= Data_i[15:8]; end Spi4CsCtrlAddr : begin Spi4CsCtrlReg[15:8] <= Data_i[15:8]; end Spi4TxFifoCtrlAddr : begin Spi4TxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi4RxFifoCtrlAddr : begin Spi4RxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi4TxFifo : begin Spi4TxFifoReg[15:8] <= Data_i[15:8]; end Spi4RxFifo : begin Spi4RxFifoReg[15:8] <= Data_i[15:8]; end Spi5CtrlAddr : begin Spi5CtrlReg[15:8] <= Data_i[15:8]; end Spi5ClkAddr : begin Spi5ClkReg[15:8] <= Data_i[15:8]; end Spi5CsDelayAddr : begin Spi5CsDelayReg[15:8] <= Data_i[15:8]; end Spi5CsCtrlAddr : begin Spi5CsCtrlReg[15:8] <= Data_i[15:8]; end Spi5TxFifoCtrlAddr : begin Spi5TxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi5RxFifoCtrlAddr : begin Spi5RxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi5TxFifo : begin Spi5TxFifoReg[15:8] <= Data_i[15:8]; end Spi5RxFifo : begin Spi5RxFifoReg[15:8] <= Data_i[15:8]; end Spi6CtrlAddr : begin Spi6CtrlReg[15:8] <= Data_i[15:8]; end Spi6ClkAddr : begin Spi6ClkReg[15:8] <= Data_i[15:8]; end Spi6CsDelayAddr : begin Spi6CsDelayReg[15:8] <= Data_i[15:8]; end Spi6CsCtrlAddr : begin Spi6CsCtrlReg[15:8] <= Data_i[15:8]; end Spi6TxFifoCtrlAddr : begin Spi6TxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi6RxFifoCtrlAddr : begin Spi6RxFifoCtrlReg[15:8] <= Data_i[15:8]; end Spi6TxFifo : begin Spi6TxFifoReg[15:8] <= Data_i[15:8]; end Spi6RxFifo : begin Spi6RxFifoReg[15:8] <= Data_i[15:8]; end SpiTxRxEn : begin SpiTxRxEnReg[15:8] <= Data_i[15:8]; end GPIOCtrlAddr : begin GPIOAReg[15:8] <= Data_i[15:8]; end GPIOCtrlAddrS : begin GPIOARegS[15:8] <= Data_i[15:8]; end Debug0Addr : begin LedReg[15:8] <= Data_i[15:8]; end endcase end 2 : begin case (Addr_i) Spi0CtrlAddr : begin Spi0CtrlReg[7:0] <= Data_i[7:0]; end Spi0ClkAddr : begin Spi0ClkReg[7:0] <= Data_i[7:0]; end Spi0CsDelayAddr : begin Spi0CsDelayReg[7:0] <= Data_i[7:0]; end Spi0CsCtrlAddr : begin Spi0CsCtrlReg[7:0] <= Data_i[7:0]; end Spi0TxFifoCtrlAddr : begin Spi0TxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi0RxFifoCtrlAddr : begin Spi0RxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi0TxFifo : begin Spi0TxFifoReg[7:0] <= Data_i[7:0]; end Spi0RxFifo : begin Spi0RxFifoReg[7:0] <= Data_i[7:0]; end Spi1CtrlAddr : begin Spi1CtrlReg[7:0] <= Data_i[7:0]; end Spi1ClkAddr : begin Spi1ClkReg[7:0] <= Data_i[7:0]; end Spi1CsDelayAddr : begin Spi1CsDelayReg[7:0] <= Data_i[7:0]; end Spi1CsCtrlAddr : begin Spi1CsCtrlReg[7:0] <= Data_i[7:0]; end Spi1TxFifoCtrlAddr : begin Spi1TxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi1RxFifoCtrlAddr : begin Spi1RxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi1TxFifo : begin Spi1TxFifoReg[7:0] <= Data_i[7:0]; end Spi1RxFifo : begin Spi1RxFifoReg[7:0] <= Data_i[7:0]; end Spi2CtrlAddr : begin Spi2CtrlReg[7:0] <= Data_i[7:0]; end Spi2ClkAddr : begin Spi2ClkReg[7:0] <= Data_i[7:0]; end Spi2CsDelayAddr : begin Spi2CsDelayReg[7:0] <= Data_i[7:0]; end Spi2CsCtrlAddr : begin Spi2CsCtrlReg[7:0] <= Data_i[7:0]; end Spi2TxFifoCtrlAddr : begin Spi2TxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi2RxFifoCtrlAddr : begin Spi2RxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi2TxFifo : begin Spi2TxFifoReg[7:0] <= Data_i[7:0]; end Spi2RxFifo : begin Spi2RxFifoReg[7:0] <= Data_i[7:0]; end Spi3CtrlAddr : begin Spi3CtrlReg[7:0] <= Data_i[7:0]; end Spi3ClkAddr : begin Spi3ClkReg[7:0] <= Data_i[7:0]; end Spi3CsDelayAddr : begin Spi3CsDelayReg[7:0] <= Data_i[7:0]; end Spi3CsCtrlAddr : begin Spi3CsCtrlReg[7:0] <= Data_i[7:0]; end Spi3TxFifoCtrlAddr : begin Spi3TxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi3RxFifoCtrlAddr : begin Spi3RxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi3TxFifo : begin Spi3TxFifoReg[7:0] <= Data_i[7:0]; end Spi3RxFifo : begin Spi3RxFifoReg[7:0] <= Data_i[7:0]; end Spi4CtrlAddr : begin Spi4CtrlReg[7:0] <= Data_i[7:0]; end Spi4ClkAddr : begin Spi4ClkReg[7:0] <= Data_i[7:0]; end Spi4CsDelayAddr : begin Spi4CsDelayReg[7:0] <= Data_i[7:0]; end Spi4CsCtrlAddr : begin Spi4CsCtrlReg[7:0] <= Data_i[7:0]; end Spi4TxFifoCtrlAddr : begin Spi4TxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi4RxFifoCtrlAddr : begin Spi4RxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi4TxFifo : begin Spi4TxFifoReg[7:0] <= Data_i[7:0]; end Spi4RxFifo : begin Spi4RxFifoReg[7:0] <= Data_i[7:0]; end Spi5CtrlAddr : begin Spi5CtrlReg[7:0] <= Data_i[7:0]; end Spi5ClkAddr : begin Spi5ClkReg[7:0] <= Data_i[7:0]; end Spi5CsDelayAddr : begin Spi5CsDelayReg[7:0] <= Data_i[7:0]; end Spi5CsCtrlAddr : begin Spi5CsCtrlReg[7:0] <= Data_i[7:0]; end Spi5TxFifoCtrlAddr : begin Spi5TxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi5RxFifoCtrlAddr : begin Spi5RxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi5TxFifo : begin Spi5TxFifoReg[7:0] <= Data_i[7:0]; end Spi5RxFifo : begin Spi5RxFifoReg[7:0] <= Data_i[7:0]; end Spi6CtrlAddr : begin Spi6CtrlReg[7:0] <= Data_i[7:0]; end Spi6ClkAddr : begin Spi6ClkReg[7:0] <= Data_i[7:0]; end Spi6CsDelayAddr : begin Spi6CsDelayReg[7:0] <= Data_i[7:0]; end Spi6CsCtrlAddr : begin Spi6CsCtrlReg[7:0] <= Data_i[7:0]; end Spi6TxFifoCtrlAddr : begin Spi6TxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi6RxFifoCtrlAddr : begin Spi6RxFifoCtrlReg[7:0] <= Data_i[7:0]; end Spi6TxFifo : begin Spi6TxFifoReg[7:0] <= Data_i[7:0]; end Spi6RxFifo : begin Spi6RxFifoReg[7:0] <= Data_i[7:0]; end SpiTxRxEn : begin SpiTxRxEnReg[7:0] <= Data_i[7:0]; end GPIOCtrlAddr : begin GPIOAReg[7:0] <= Data_i[7:0]; end GPIOCtrlAddrS : begin GPIOARegS[7:0] <= Data_i[7:0]; end Debug0Addr : begin LedReg[7:0] <= Data_i[7:0]; end endcase end endcase end end end always @(*) begin if (Rst_i) begin ansReg = 0; end else begin if (Val_i) begin case(SmcBe_i) 0 : begin case (Addr_i) Spi0CtrlAddr : begin ansReg = Spi0CtrlReg; end Spi0ClkAddr : begin ansReg = Spi0ClkReg; end Spi0CsDelayAddr : begin ansReg = Spi0CsDelayReg; end Spi0CsCtrlAddr : begin ansReg = Spi0CsCtrlReg; end Spi0TxFifoCtrlAddr : begin ansReg = Spi0TxFifoCtrlReg; end Spi0RxFifoCtrlAddr : begin ansReg = Spi0RxFifoCtrlReg; end Spi0TxFifo : begin ansReg = Spi0TxFifoReg; end Spi0RxFifo : begin ansReg = Spi0RxFifoReg; end Spi1CtrlAddr : begin ansReg = Spi1CtrlReg; end Spi1ClkAddr : begin ansReg = Spi1ClkReg; end Spi1CsDelayAddr : begin ansReg = Spi1CsDelayReg; end Spi1CsCtrlAddr : begin ansReg = Spi1CsCtrlReg; end Spi1TxFifoCtrlAddr : begin ansReg = Spi1TxFifoCtrlReg; end Spi1RxFifoCtrlAddr : begin ansReg = Spi1RxFifoCtrlReg; end Spi1TxFifo : begin ansReg = Spi1TxFifoReg; end Spi1RxFifo : begin ansReg = Spi1RxFifoReg; end Spi2CtrlAddr : begin ansReg = Spi2CtrlReg; end Spi2ClkAddr : begin ansReg = Spi2ClkReg; end Spi2CsDelayAddr : begin ansReg = Spi2CsDelayReg; end Spi2CsCtrlAddr : begin ansReg = Spi2CsCtrlReg; end Spi2TxFifoCtrlAddr : begin ansReg = Spi2TxFifoCtrlReg; end Spi2RxFifoCtrlAddr : begin ansReg = Spi2RxFifoCtrlReg; end Spi2TxFifo : begin ansReg = Spi2TxFifoReg; end Spi2RxFifo : begin ansReg = Spi2RxFifoReg; end Spi3CtrlAddr : begin ansReg = Spi3CtrlReg; end Spi3ClkAddr : begin ansReg = Spi3ClkReg; end Spi3CsDelayAddr : begin ansReg = Spi3CsDelayReg; end Spi3CsCtrlAddr : begin ansReg = Spi3CsCtrlReg; end Spi3TxFifoCtrlAddr : begin ansReg = Spi3TxFifoCtrlReg; end Spi3RxFifoCtrlAddr : begin ansReg = Spi3RxFifoCtrlReg; end Spi3TxFifo : begin ansReg = Spi3TxFifoReg; end Spi3RxFifo : begin ansReg = Spi3RxFifoReg; end Spi4CtrlAddr : begin ansReg = Spi4CtrlReg; end Spi4ClkAddr : begin ansReg = Spi4ClkReg; end Spi4CsDelayAddr : begin ansReg = Spi4CsDelayReg; end Spi4CsCtrlAddr : begin ansReg = Spi4CsCtrlReg; end Spi4TxFifoCtrlAddr : begin ansReg = Spi4TxFifoCtrlReg; end Spi4RxFifoCtrlAddr : begin ansReg = Spi4RxFifoCtrlReg; end Spi4TxFifo : begin ansReg = Spi4TxFifoReg; end Spi4RxFifo : begin ansReg = Spi4RxFifoReg; end Spi5CtrlAddr : begin ansReg = Spi5CtrlReg; end Spi5ClkAddr : begin ansReg = Spi5ClkReg; end Spi5CsDelayAddr : begin ansReg = Spi5CsDelayReg; end Spi5CsCtrlAddr : begin ansReg = Spi5CsCtrlReg; end Spi5TxFifoCtrlAddr : begin ansReg = Spi5TxFifoCtrlReg; end Spi5RxFifoCtrlAddr : begin ansReg = Spi5RxFifoCtrlReg; end Spi5TxFifo : begin ansReg = Spi5TxFifoReg; end Spi5RxFifo : begin ansReg = Spi5RxFifoReg; end Spi6CtrlAddr : begin ansReg = Spi6CtrlReg; end Spi6ClkAddr : begin ansReg = Spi6ClkReg; end Spi6CsDelayAddr : begin ansReg = Spi6CsDelayReg; end Spi6CsCtrlAddr : begin ansReg = Spi6CsCtrlReg; end Spi6TxFifoCtrlAddr : begin ansReg = Spi6TxFifoCtrlReg; end Spi6RxFifoCtrlAddr : begin ansReg = Spi6RxFifoCtrlReg; end Spi6TxFifo : begin ansReg = Spi6TxFifoReg; end Spi6RxFifo : begin ansReg = Spi6RxFifoReg; end SpiTxRxEn : begin ansReg = SpiTxRxEnReg; end GPIOCtrlAddr : begin ansReg = GPIOAReg; end GPIOCtrlAddrS : begin ansReg = GPIOARegS; end Debug0Addr : begin ansReg = LedReg; end endcase end 1 : begin case (Addr_i) Spi0CtrlAddr : begin ansReg = Spi0CtrlReg[15:8]; end Spi0ClkAddr : begin ansReg = Spi0ClkReg[15:8]; end Spi0CsDelayAddr : begin ansReg = Spi0CsDelayReg[15:8]; end Spi0CsCtrlAddr : begin ansReg = Spi0CsCtrlReg[15:8]; end Spi0TxFifoCtrlAddr : begin ansReg = Spi0TxFifoCtrlReg[15:8]; end Spi0RxFifoCtrlAddr : begin ansReg = Spi0RxFifoCtrlReg[15:8]; end Spi0TxFifo : begin ansReg = Spi0TxFifoReg[15:8]; end Spi0RxFifo : begin ansReg = Spi0RxFifoReg[15:8]; end Spi1CtrlAddr : begin ansReg = Spi1CtrlReg[15:8]; end Spi1ClkAddr : begin ansReg = Spi1ClkReg[15:8]; end Spi1CsDelayAddr : begin ansReg = Spi1CsDelayReg[15:8]; end Spi1CsCtrlAddr : begin ansReg = Spi1CsCtrlReg[15:8]; end Spi1TxFifoCtrlAddr : begin ansReg = Spi1TxFifoCtrlReg[15:8]; end Spi1RxFifoCtrlAddr : begin ansReg = Spi1RxFifoCtrlReg[15:8]; end Spi1TxFifo : begin ansReg = Spi1TxFifoReg[15:8]; end Spi1RxFifo : begin ansReg = Spi1RxFifoReg[15:8]; end Spi2CtrlAddr : begin ansReg = Spi2CtrlReg[15:8]; end Spi2ClkAddr : begin ansReg = Spi2ClkReg[15:8]; end Spi2CsDelayAddr : begin ansReg = Spi2CsDelayReg[15:8]; end Spi2CsCtrlAddr : begin ansReg = Spi2CsCtrlReg[15:8]; end Spi2TxFifoCtrlAddr : begin ansReg = Spi2TxFifoCtrlReg[15:8]; end Spi2RxFifoCtrlAddr : begin ansReg = Spi2RxFifoCtrlReg[15:8]; end Spi2TxFifo : begin ansReg = Spi2TxFifoReg[15:8]; end Spi2RxFifo : begin ansReg = Spi2RxFifoReg[15:8]; end Spi3CtrlAddr : begin ansReg = Spi3CtrlReg[15:8]; end Spi3ClkAddr : begin ansReg = Spi3ClkReg[15:8]; end Spi3CsDelayAddr : begin ansReg = Spi3CsDelayReg[15:8]; end Spi3CsCtrlAddr : begin ansReg = Spi3CsCtrlReg[15:8]; end Spi3TxFifoCtrlAddr : begin ansReg = Spi3TxFifoCtrlReg[15:8]; end Spi3RxFifoCtrlAddr : begin ansReg = Spi3RxFifoCtrlReg[15:8]; end Spi3TxFifo : begin ansReg = Spi3TxFifoReg[15:8]; end Spi3RxFifo : begin ansReg = Spi3RxFifoReg[15:8]; end Spi4CtrlAddr : begin ansReg = Spi4CtrlReg[15:8]; end Spi4ClkAddr : begin ansReg = Spi4ClkReg[15:8]; end Spi4CsDelayAddr : begin ansReg = Spi4CsDelayReg[15:8]; end Spi4CsCtrlAddr : begin ansReg = Spi4CsCtrlReg[15:8]; end Spi4TxFifoCtrlAddr : begin ansReg = Spi4TxFifoCtrlReg[15:8]; end Spi4RxFifoCtrlAddr : begin ansReg = Spi4RxFifoCtrlReg[15:8]; end Spi4TxFifo : begin ansReg = Spi4TxFifoReg[15:8]; end Spi4RxFifo : begin ansReg = Spi4RxFifoReg[15:8]; end Spi5CtrlAddr : begin ansReg = Spi5CtrlReg[15:8]; end Spi5ClkAddr : begin ansReg = Spi5ClkReg[15:8]; end Spi5CsDelayAddr : begin ansReg = Spi5CsDelayReg[15:8]; end Spi5CsCtrlAddr : begin ansReg = Spi5CsCtrlReg[15:8]; end Spi5TxFifoCtrlAddr : begin ansReg = Spi5TxFifoCtrlReg[15:8]; end Spi5RxFifoCtrlAddr : begin ansReg = Spi5RxFifoCtrlReg[15:8]; end Spi5TxFifo : begin ansReg = Spi5TxFifoReg[15:8]; end Spi5RxFifo : begin ansReg = Spi5RxFifoReg[15:8]; end Spi6CtrlAddr : begin ansReg = Spi6CtrlReg[15:8]; end Spi6ClkAddr : begin ansReg = Spi6ClkReg[15:8]; end Spi6CsDelayAddr : begin ansReg = Spi6CsDelayReg[15:8]; end Spi6CsCtrlAddr : begin ansReg = Spi6CsCtrlReg[15:8]; end Spi6TxFifoCtrlAddr : begin ansReg = Spi6TxFifoCtrlReg[15:8]; end Spi6RxFifoCtrlAddr : begin ansReg = Spi6RxFifoCtrlReg[15:8]; end Spi6TxFifo : begin ansReg = Spi6TxFifoReg[15:8]; end Spi6RxFifo : begin ansReg = Spi6RxFifoReg[15:8]; end SpiTxRxEn : begin ansReg = SpiTxRxEnReg[15:8]; end GPIOCtrlAddr : begin ansReg = GPIOAReg[15:8]; end GPIOCtrlAddrS : begin ansReg = GPIOARegS[15:8]; end Debug0Addr : begin ansReg = LedReg[15:8]; end endcase end 2 : begin case (Addr_i) Spi0CtrlAddr : begin ansReg = Spi0CtrlReg[7:0]; end Spi0ClkAddr : begin ansReg = Spi0ClkReg[7:0]; end Spi0CsDelayAddr : begin ansReg = Spi0CsDelayReg[7:0]; end Spi0CsCtrlAddr : begin ansReg = Spi0CsCtrlReg[7:0]; end Spi0TxFifoCtrlAddr : begin ansReg = Spi0TxFifoCtrlReg[7:0]; end Spi0RxFifoCtrlAddr : begin ansReg = Spi0RxFifoCtrlReg[7:0]; end Spi0TxFifo : begin ansReg = Spi0TxFifoReg[7:0]; end Spi0RxFifo : begin ansReg = Spi0RxFifoReg[7:0]; end Spi1CtrlAddr : begin ansReg = Spi1CtrlReg[7:0]; end Spi1ClkAddr : begin ansReg = Spi1ClkReg[7:0]; end Spi1CsDelayAddr : begin ansReg = Spi1CsDelayReg[7:0]; end Spi1CsCtrlAddr : begin ansReg = Spi1CsCtrlReg[7:0]; end Spi1TxFifoCtrlAddr : begin ansReg = Spi1TxFifoCtrlReg[7:0]; end Spi1RxFifoCtrlAddr : begin ansReg = Spi1RxFifoCtrlReg[7:0]; end Spi1TxFifo : begin ansReg = Spi1TxFifoReg[7:0]; end Spi1RxFifo : begin ansReg = Spi1RxFifoReg[7:0]; end Spi2CtrlAddr : begin ansReg = Spi2CtrlReg[7:0]; end Spi2ClkAddr : begin ansReg = Spi2ClkReg[7:0]; end Spi2CsDelayAddr : begin ansReg = Spi2CsDelayReg[7:0]; end Spi2CsCtrlAddr : begin ansReg = Spi2CsCtrlReg[7:0]; end Spi2TxFifoCtrlAddr : begin ansReg = Spi2TxFifoCtrlReg[7:0]; end Spi2RxFifoCtrlAddr : begin ansReg = Spi2RxFifoCtrlReg[7:0]; end Spi2TxFifo : begin ansReg = Spi2TxFifoReg[7:0]; end Spi2RxFifo : begin ansReg = Spi2RxFifoReg[7:0]; end Spi3CtrlAddr : begin ansReg = Spi3CtrlReg[7:0]; end Spi3ClkAddr : begin ansReg = Spi3ClkReg[7:0]; end Spi3CsDelayAddr : begin ansReg = Spi3CsDelayReg[7:0]; end Spi3CsCtrlAddr : begin ansReg = Spi3CsCtrlReg[7:0]; end Spi3TxFifoCtrlAddr : begin ansReg = Spi3TxFifoCtrlReg[7:0]; end Spi3RxFifoCtrlAddr : begin ansReg = Spi3RxFifoCtrlReg[7:0]; end Spi3TxFifo : begin ansReg = Spi3TxFifoReg[7:0]; end Spi3RxFifo : begin ansReg = Spi3RxFifoReg[7:0]; end Spi4CtrlAddr : begin ansReg = Spi4CtrlReg[7:0]; end Spi4ClkAddr : begin ansReg = Spi4ClkReg[7:0]; end Spi4CsDelayAddr : begin ansReg = Spi4CsDelayReg[7:0]; end Spi4CsCtrlAddr : begin ansReg = Spi4CsCtrlReg[7:0]; end Spi4TxFifoCtrlAddr : begin ansReg = Spi4TxFifoCtrlReg[7:0]; end Spi4RxFifoCtrlAddr : begin ansReg = Spi4RxFifoCtrlReg[7:0]; end Spi4TxFifo : begin ansReg = Spi4TxFifoReg[7:0]; end Spi4RxFifo : begin ansReg = Spi4RxFifoReg[7:0]; end Spi5CtrlAddr : begin ansReg = Spi5CtrlReg[7:0]; end Spi5ClkAddr : begin ansReg = Spi5ClkReg[7:0]; end Spi5CsDelayAddr : begin ansReg = Spi5CsDelayReg[7:0]; end Spi5CsCtrlAddr : begin ansReg = Spi5CsCtrlReg[7:0]; end Spi5TxFifoCtrlAddr : begin ansReg = Spi5TxFifoCtrlReg[7:0]; end Spi5RxFifoCtrlAddr : begin ansReg = Spi5RxFifoCtrlReg[7:0]; end Spi5TxFifo : begin ansReg = Spi5TxFifoReg[7:0]; end Spi5RxFifo : begin ansReg = Spi5RxFifoReg[7:0]; end Spi6CtrlAddr : begin ansReg = Spi6CtrlReg[7:0]; end Spi6ClkAddr : begin ansReg = Spi6ClkReg[7:0]; end Spi6CsDelayAddr : begin ansReg = Spi6CsDelayReg[7:0]; end Spi6CsCtrlAddr : begin ansReg = Spi6CsCtrlReg[7:0]; end Spi6TxFifoCtrlAddr : begin ansReg = Spi6TxFifoCtrlReg[7:0]; end Spi6RxFifoCtrlAddr : begin ansReg = Spi6RxFifoCtrlReg[7:0]; end Spi6TxFifo : begin ansReg = Spi6TxFifoReg[7:0]; end Spi6RxFifo : begin ansReg = Spi6RxFifoReg[7:0]; end SpiTxRxEn : begin ansReg = SpiTxRxEnReg[7:0]; end GPIOCtrlAddr : begin ansReg = GPIOAReg[7:0]; end GPIOCtrlAddrS : begin ansReg = GPIOARegS[7:0]; end Debug0Addr : begin ansReg = LedReg[7:0]; end endcase end endcase end end end endmodule