module ClkCh (
    input Rst_i,
    input clkCh,
    input clkOutMMCM,
    input clkMan,

    output reg SpiClk_o



);



always @(*) begin 
    if (Rst_i) begin 
        SpiClk_o = 0;
    end
    else begin 
        if (clkCh) begin 
            SpiClk_o = clkOutMMCM;
        end
        else begin 
            SpiClk_o = clkMan;
        end
    end
end










endmodule