`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 10/30/2023 11:24:31 AM // Design Name: // Module Name: S5443_3Top // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module S5443_3Top #( parameter CmdRegWidth = 32, parameter AddrRegWidth = 12, parameter SpiNum = 7 ) ( input Clk123_i, input [AddrRegWidth-2:0] SmcAddr_i, inout [CmdRegWidth/2-1:0] SmcData_i, input SmcAwe_i, input SmcAmsN_i, input SmcAre_i, input [1:0] SmcBe_i, input SmcAoe_i, output [SpiNum-1:0] Ld_i, output Led_o, output [SpiNum-1:0] Mosi0_o, output [SpiNum-1:0] Mosi1_o, output [SpiNum-1:0] Mosi2_o, output [SpiNum-1:0] Mosi3_o, output [SpiNum-1:0] Ss_o, output [SpiNum-1:0] SsFlash_o, output [SpiNum-1:0] Sck_o, output [SpiNum-1:0] SpiRst_o, output LD_o ); //================================================================================ // REG/WIRE //================================================================================ wire Clk100_i; wire [SpiNum-1:0]Sck; wire [AddrRegWidth-1:0] addr; wire [SpiNum-1:0] Ss; wire [SpiNum-1:0]Mosi0; wire [SpiNum-1:0]Mosi1; wire [SpiNum-1:0]Mosi2; wire [SpiNum-1:0]Mosi3; wire [SpiNum-1:0] ten; wire clk80; wire clk61; wire initRst; wire gclk; wire [0:7] baudRate [SpiNum-1:0]; //SPI0 wire [CmdRegWidth-1:0] spi0Ctrl; wire [CmdRegWidth-1:0] spi0Clk; wire [CmdRegWidth-1:0] spi0CsDelay; wire [CmdRegWidth-1:0] spi0CsCtrl; wire [CmdRegWidth-1:0] spi0TxFifoCtrl; wire [CmdRegWidth-1:0] spi0RxFifoCtrl; wire [CmdRegWidth-1:0] spi0TxFifo; wire [CmdRegWidth-1:0] spi0RxFifo; //SPI1 wire [CmdRegWidth-1:0] spi1Ctrl; wire [CmdRegWidth-1:0] spi1Clk; wire [CmdRegWidth-1:0] spi1CsDelay; wire [CmdRegWidth-1:0] spi1CsCtrl; wire [CmdRegWidth-1:0] spi1TxFifoCtrl; wire [CmdRegWidth-1:0] spi1RxFifoCtrl; wire [CmdRegWidth-1:0] spi1TxFifo; wire [CmdRegWidth-1:0] spi1RxFifo; //SPI2 wire [CmdRegWidth-1:0] spi2Ctrl; wire [CmdRegWidth-1:0] spi2Clk; wire [CmdRegWidth-1:0] spi2CsDelay; wire [CmdRegWidth-1:0] spi2CsCtrl; wire [CmdRegWidth-1:0] spi2TxFifoCtrl; wire [CmdRegWidth-1:0] spi2RxFifoCtrl; wire [CmdRegWidth-1:0] spi2TxFifo; wire [CmdRegWidth-1:0] Spi2RxFifo; //SPI3 wire [CmdRegWidth-1:0] spi3Ctrl; wire [CmdRegWidth-1:0] spi3Clk; wire [CmdRegWidth-1:0] spi3CsDelay; wire [CmdRegWidth-1:0] spi3CsCtrl; wire [CmdRegWidth-1:0] spi3TxFifoCtrl; wire [CmdRegWidth-1:0] spi3RxFifoCtrl; wire [CmdRegWidth-1:0] Spi3TxFifo; wire [CmdRegWidth-1:0] Spi3RxFifo; //SPI4 wire [CmdRegWidth-1:0] spi4Ctrl; wire [CmdRegWidth-1:0] spi4Clk; wire [CmdRegWidth-1:0] spi4CsDelay; wire [CmdRegWidth-1:0] spi4CsCtrl; wire [CmdRegWidth-1:0] spi4TxFifoCtrl; wire [CmdRegWidth-1:0] spi4RxFifoCtrl; wire [CmdRegWidth-1:0] Spi4TxFifo; wire [CmdRegWidth-1:0] Spi4RxFifo; //SPI5 wire [CmdRegWidth-1:0] spi5Ctrl; wire [CmdRegWidth-1:0] spi5Clk; wire [CmdRegWidth-1:0] spi5CsDelay; wire [CmdRegWidth-1:0] spi5CsCtrl; wire [CmdRegWidth-1:0] spi5TxFifoCtrl; wire [CmdRegWidth-1:0] spi5RxFifoCtrl; wire [CmdRegWidth-1:0] Spi5TxFifo; wire [CmdRegWidth-1:0] Spi5RxFifo; //SPI6 wire [CmdRegWidth-1:0] spi6Ctrl; wire [CmdRegWidth-1:0] spi6Clk; wire [CmdRegWidth-1:0] spi6CsDelay; wire [CmdRegWidth-1:0] spi6CsCtrl; wire [CmdRegWidth-1:0] spi6TxFifoCtrl; wire [CmdRegWidth-1:0] spi6RxFifoCtrl; wire [CmdRegWidth-1:0] Spi6TxFifo; wire [CmdRegWidth-1:0] Spi6RxFifo; wire [CmdRegWidth-1:0] SpiTxRxEn; wire [CmdRegWidth-1:0] GPIOA; wire [AddrRegWidth-1:0] toRegMapAddr; wire [CmdRegWidth/2-1:0] toRegMapData; wire toRegMapVal; wire [SpiNum-1:0] toFifoVal; wire [CmdRegWidth*SpiNum-1:0] toFifoData; wire [SpiNum-1:0] toSpiVal; wire [0:31] toSpiData [SpiNum-1:0]; wire [0:1] widthSel [SpiNum-1:0]; wire [SpiNum-1:0] CPOL; wire [SpiNum-1:0] CPHA; wire [SpiNum-1:0] endianSel; wire [SpiNum-1:0] selSt; wire [SpiNum-1:0] spiMode; wire [0:5] stopDelay [SpiNum-1:0]; wire [SpiNum-1:0] leadx; wire [SpiNum-1:0] lag; wire [SpiNum-1:0] fifoRxRst; wire [SpiNum-1:0] fifoTxRst; wire [0:7] wordCntTx [SpiNum-1:0]; wire [0:7] wordCntRx [SpiNum-1:0]; wire [SpiNum-1:0] CS0; wire [SpiNum-1:0] CS1; wire [SpiNum-1:0] Assel; wire [SpiNum-1:0] spiClkBus; wire [SpiNum-1:0] spiSyncRst; wire [AddrRegWidth-1:0] smcAddr; wire [CmdRegWidth/2-1:0] smcData; wire smcVal; //RxFifo wire [0:31] dataToRxFifo [SpiNum-1:0]; wire [0:7] addrToRxFifo [SpiNum-1:0]; wire [SpiNum-1:0] valToRxFifo; wire [SpiNum-1:0] valToTxFifoRead; // SPI mode choice wire [SpiNum-1:0] SckR; wire [SpiNum-1:0] SsR; wire [SpiNum-1:0] Mosi0R; wire [SpiNum-1:0] valReg; wire [SpiNum-1:0] valToTxR; wire [SpiNum-1:0] valToRxR; wire [0:31] dataToRxFifoR [SpiNum-1:0]; wire [SpiNum-1:0] SckQ; wire [SpiNum-1:0] SsQ; wire [SpiNum-1:0] Mosi0Q; wire [SpiNum-1:0] valToTxQ; wire [SpiNum-1:0] valToRxQ; wire [0:31] dataToRxFifoQ [SpiNum-1:0]; wire [0:31] dataFromRxFifo [SpiNum-1:0]; wire [CmdRegWidth/2-1:0] muxedData; wire Clk100_o; wire Clk40_o; wire [CmdRegWidth/2-1:0] ansData; //================================================================================ // ASSIGNMENTS //================================================================================ assign ten = SpiTxRxEn[6:0]; assign Mosi1_o = Mosi1; assign Mosi2_o = Mosi2; assign Mosi3_o = Mosi3; assign Ss_o[0] = (Assel[0])? ((CS0[0])? Ss[0]:~Ss[0]):CS0[0]; assign Ss_o[1] = (Assel[1])? ((CS0[1])? Ss[1]:~Ss[1]):CS0[1]; assign Ss_o[2] = (Assel[2])? ((CS0[2])? Ss[2]:~Ss[2]):CS0[2]; assign Ss_o[3] = (Assel[3])? ((CS0[3])? Ss[3]:~Ss[3]):CS0[3]; assign Ss_o[4] = (Assel[4])? ((CS0[4])? Ss[4]:~Ss[4]):CS0[4]; assign Ss_o[5] = (Assel[5])? ((CS0[5])? Ss[5]:~Ss[5]):CS0[5]; assign Ss_o[6] = (Assel[6])? ((CS0[6])? Ss[6]:~Ss[6]):CS0[6]; assign SsFlash_o[0] = (Assel[0])?(CS1[0]? Ss[0]:~Ss[0]):CS1[0]; assign SsFlash_o[1] = (Assel[1])?(CS1[1]? Ss[1]:~Ss[1]):CS1[1]; assign SsFlash_o[2] = (Assel[2])?(CS1[2]? Ss[2]:~Ss[2]):CS1[2]; assign SsFlash_o[3] = (Assel[3])?(CS1[3]? Ss[3]:~Ss[3]):CS1[3]; assign SsFlash_o[4] = (Assel[4])?(CS1[4]? Ss[4]:~Ss[4]):CS1[4]; assign SsFlash_o[5] = (Assel[5])?(CS1[5]? Ss[5]:~Ss[5]):CS1[5]; assign SsFlash_o[6] = (Assel[6])?(CS1[6]? Ss[6]:~Ss[6]):CS1[6]; assign Sck_o = Sck; assign widthSel[0] = spi0Ctrl[6:5]; assign widthSel[1] = spi1Ctrl[6:5]; assign widthSel[2] = spi2Ctrl[6:5]; assign widthSel[3] = spi3Ctrl[6:5]; assign widthSel[4] = spi4Ctrl[6:5]; assign widthSel[5] = spi5Ctrl[6:5]; assign widthSel[6] = spi6Ctrl[6:5]; assign spiMode[0] = spi0Ctrl[7]; assign spiMode[1] = spi1Ctrl[7]; assign spiMode[2] = spi2Ctrl[7]; assign spiMode[3] = spi3Ctrl[7]; assign spiMode[4] = spi4Ctrl[7]; assign spiMode[5] = spi5Ctrl[7]; assign spiMode[6] = spi6Ctrl[7]; assign CPOL[0] = spi0Ctrl[2]; assign CPOL[1] = spi1Ctrl[2]; assign CPOL[2] = spi2Ctrl[2]; assign CPOL[3] = spi3Ctrl[2]; assign CPOL[4] = spi4Ctrl[2]; assign CPOL[5] = spi5Ctrl[2]; assign CPOL[6] = spi6Ctrl[2]; assign CPHA[0] = spi0Ctrl[1]; assign CPHA[1] = spi1Ctrl[1]; assign CPHA[2] = spi2Ctrl[1]; assign CPHA[3] = spi3Ctrl[1]; assign CPHA[4] = spi4Ctrl[1]; assign CPHA[5] = spi5Ctrl[1]; assign CPHA[6] = spi6Ctrl[1]; assign endianSel[0] = spi0Ctrl[8]; assign endianSel[1] = spi1Ctrl[8]; assign endianSel[2] = spi2Ctrl[8]; assign endianSel[3] = spi3Ctrl[8]; assign endianSel[4] = spi4Ctrl[8]; assign endianSel[5] = spi5Ctrl[8]; assign endianSel[6] = spi6Ctrl[8]; assign selSt[0] = spi0Ctrl[4]; assign selSt[1] = spi1Ctrl[4]; assign selSt[2] = spi2Ctrl[4]; assign selSt[3] = spi3Ctrl[4]; assign selSt[4] = spi4Ctrl[4]; assign selSt[5] = spi5Ctrl[4]; assign selSt[6] = spi6Ctrl[4]; assign Assel[0] = spi0Ctrl[3]; assign Assel[1] = spi1Ctrl[3]; assign Assel[2] = spi2Ctrl[3]; assign Assel[3] = spi3Ctrl[3]; assign Assel[4] = spi4Ctrl[3]; assign Assel[5] = spi5Ctrl[3]; assign Assel[6] = spi6Ctrl[3]; assign stopDelay[0] = spi0CsDelay[7:2]; assign stopDelay[1] = spi1CsDelay[7:2]; assign stopDelay[2] = spi2CsDelay[7:2]; assign stopDelay[3] = spi3CsDelay[7:2]; assign stopDelay[4] = spi4CsDelay[7:2]; assign stopDelay[5] = spi5CsDelay[7:2]; assign stopDelay[6] = spi6CsDelay[7:2]; assign leadx[0] = spi0CsDelay[1]; assign leadx[1] = spi1CsDelay[1]; assign leadx[2] = spi2CsDelay[1]; assign leadx[3] = spi3CsDelay[1]; assign leadx[4] = spi4CsDelay[1]; assign leadx[5] = spi5CsDelay[1]; assign leadx[6] = spi6CsDelay[1]; assign lag[0] = spi0CsDelay[0]; assign lag[1] = spi1CsDelay[0]; assign lag[2] = spi2CsDelay[0]; assign lag[3] = spi3CsDelay[0]; assign lag[4] = spi4CsDelay[0]; assign lag[5] = spi5CsDelay[0]; assign lag[6] = spi6CsDelay[0]; assign baudRate[0] = spi0Clk[7:0]; assign baudRate[1] = spi1Clk[7:0]; assign baudRate[2] = spi2Clk[7:0]; assign baudRate[3] = spi3Clk[7:0]; assign baudRate[4] = spi4Clk[7:0]; assign baudRate[5] = spi5Clk[7:0]; assign baudRate[6] = spi6Clk[7:0]; assign SpiRst_o[0] = GPIOA[0]; assign SpiRst_o[1] = GPIOA[1]; assign SpiRst_o[2] = GPIOA[2]; assign SpiRst_o[3] = GPIOA[3]; assign SpiRst_o[4] = GPIOA[4]; assign SpiRst_o[5] = GPIOA[5]; assign SpiRst_o[6] = GPIOA[6]; assign fifoRxRst[0] = spi0RxFifoCtrl[0]; assign fifoRxRst[1] = spi1RxFifoCtrl[0]; assign fifoRxRst[2] = spi2RxFifoCtrl[0]; assign fifoRxRst[3] = spi3RxFifoCtrl[0]; assign fifoRxRst[4] = spi4RxFifoCtrl[0]; assign fifoRxRst[5] = spi5RxFifoCtrl[0]; assign fifoRxRst[6] = spi6RxFifoCtrl[0]; assign fifoTxRst[0] = spi0TxFifoCtrl[0]; assign fifoTxRst[1] = spi1TxFifoCtrl[0]; assign fifoTxRst[2] = spi2TxFifoCtrl[0]; assign fifoTxRst[3] = spi3TxFifoCtrl[0]; assign fifoTxRst[4] = spi4TxFifoCtrl[0]; assign fifoTxRst[5] = spi5TxFifoCtrl[0]; assign fifoTxRst[6] = spi6TxFifoCtrl[0]; assign Ld_i[0] = GPIOA[16]; assign Ld_i[1] = GPIOA[17]; assign Ld_i[2] = GPIOA[18]; assign Ld_i[3] = GPIOA[19]; assign Ld_i[4] = GPIOA[20]; assign Ld_i[5] = GPIOA[21]; assign Ld_i[6] = GPIOA[22]; assign LD_o = Ld_i[0]&Ld_i[1]&Ld_i[2]&Ld_i[3]&Ld_i[4]&Ld_i[5]&Ld_i[6]; assign wordCntRx[0] = spi0RxFifoCtrl[15:8]; assign wordCntRx[1] = spi1RxFifoCtrl[15:8]; assign wordCntRx[2] = spi2RxFifoCtrl[15:8]; assign wordCntRx[3] = spi3RxFifoCtrl[15:8]; assign wordCntRx[4] = spi4RxFifoCtrl[15:8]; assign wordCntRx[5] = spi5RxFifoCtrl[15:8]; assign wordCntRx[6] = spi6RxFifoCtrl[15:8]; assign wordCntTx[0] = spi0TxFifoCtrl[15:8]; assign wordCntTx[1] = spi1TxFifoCtrl[15:8]; assign wordCntTx[2] = spi2TxFifoCtrl[15:8]; assign wordCntTx[3] = spi3TxFifoCtrl[15:8]; assign wordCntTx[4] = spi4TxFifoCtrl[15:8]; assign wordCntTx[5] = spi5TxFifoCtrl[15:8]; assign wordCntTx[6] = spi6TxFifoCtrl[15:8]; assign CS0[0] = spi0CsCtrl[0]; assign CS0[1] = spi1CsCtrl[0]; assign CS0[2] = spi2CsCtrl[0]; assign CS0[3] = spi3CsCtrl[0]; assign CS0[4] = spi4CsCtrl[0]; assign CS0[5] = spi5CsCtrl[0]; assign CS0[6] = spi6CsCtrl[0]; assign CS1[0] = spi0CsCtrl[1]; assign CS1[1] = spi1CsCtrl[1]; assign CS1[2] = spi2CsCtrl[1]; assign CS1[3] = spi3CsCtrl[1]; assign CS1[4] = spi4CsCtrl[1]; assign CS1[5] = spi5CsCtrl[1]; assign CS1[6] = spi6CsCtrl[1]; assign Ss[0] = (spiMode)? SsQ[0]:SsR[0]; assign Ss[1] = (spiMode)? SsQ[1]:SsR[1]; assign Ss[2] = (spiMode)? SsQ[2]:SsR[2]; assign Ss[3] = (spiMode)? SsQ[3]:SsR[3]; assign Ss[4] = (spiMode)? SsQ[4]:SsR[4]; assign Ss[5] = (spiMode)? SsQ[5]:SsR[5]; assign Ss[6] = (spiMode)? SsQ[6]:SsR[6]; assign Sck[0] = (spiMode)? SckQ[0]:SckR[0]; assign Sck[1] = (spiMode)? SckQ[1]:SckR[1]; assign Sck[2] = (spiMode)? SckQ[2]:SckR[2]; assign Sck[3] = (spiMode)? SckQ[3]:SckR[3]; assign Sck[4] = (spiMode)? SckQ[4]:SckR[4]; assign Sck[5] = (spiMode)? SckQ[5]:SckR[5]; assign Sck[6] = (spiMode)? SckQ[6]:SckR[6]; assign Mosi0[0] = (spiMode)? Mosi0Q[0]:Mosi0R[0]; assign Mosi0[1] = (spiMode)? Mosi0Q[1]:Mosi0R[1]; assign Mosi0[2] = (spiMode)? Mosi0Q[2]:Mosi0R[2]; assign Mosi0[3] = (spiMode)? Mosi0Q[3]:Mosi0R[3]; assign Mosi0[4] = (spiMode)? Mosi0Q[4]:Mosi0R[4]; assign Mosi0[5] = (spiMode)? Mosi0Q[5]:Mosi0R[5]; assign Mosi0[6] = (spiMode)? Mosi0Q[6]:Mosi0R[6]; assign valToTxFifoRead[0] = (spiMode)? valToTxQ[0]:valToTxR[0]; assign valToTxFifoRead[1] = (spiMode)? valToTxQ[1]:valToTxR[1]; assign valToTxFifoRead[2] = (spiMode)? valToTxQ[2]:valToTxR[2]; assign valToTxFifoRead[3] = (spiMode)? valToTxQ[3]:valToTxR[3]; assign valToTxFifoRead[4] = (spiMode)? valToTxQ[4]:valToTxR[4]; assign valToTxFifoRead[5] = (spiMode)? valToTxQ[5]:valToTxR[5]; assign valToTxFifoRead[6] = (spiMode)? valToTxQ[6]:valToTxR[6]; assign valToRxFifo[0] = (spiMode)? valToRxQ[0]:valToRxR[0]; assign valToRxFifo[1] = (spiMode)? valToRxQ[1]:valToRxR[1]; assign valToRxFifo[2] = (spiMode)? valToRxQ[2]:valToRxR[2]; assign valToRxFifo[3] = (spiMode)? valToRxQ[3]:valToRxR[3]; assign valToRxFifo[4] = (spiMode)? valToRxQ[4]:valToRxR[4]; assign valToRxFifo[5] = (spiMode)? valToRxQ[5]:valToRxR[5]; assign valToRxFifo[6] = (spiMode)? valToRxQ[6]:valToRxR[6]; assign dataToRxFifo[0] = (spiMode)? dataToRxFifoQ[0]:dataToRxFifoR[0]; assign dataToRxFifo[1] = (spiMode)? dataToRxFifoQ[1]:dataToRxFifoR[1]; assign dataToRxFifo[2] = (spiMode)? dataToRxFifoQ[2]:dataToRxFifoR[2]; assign dataToRxFifo[3] = (spiMode)? dataToRxFifoQ[3]:dataToRxFifoR[3]; assign dataToRxFifo[4] = (spiMode)? dataToRxFifoQ[4]:dataToRxFifoR[4]; assign dataToRxFifo[5] = (spiMode)? dataToRxFifoQ[5]:dataToRxFifoR[5]; assign dataToRxFifo[6] = (spiMode)? dataToRxFifoQ[6]:dataToRxFifoR[6]; // assign SmcData_i = (!SmcAoe_i)?muxedData:16'bz; //================================================================================ // CODING //================================================================================ DataOutMux DataOutMuxer ( // .Rst_i (initRst), .Addr_i (smcAddr), .ToRegMapAddr_i (toRegMapAddr), .DataFromRegMap_i (ansData), .DataFromRxFifo1_i (dataFromRxFifo[0]), .DataFromRxFifo2_i (dataFromRxFifo[1]), .DataFromRxFifo3_i (dataFromRxFifo[2]), .DataFromRxFifo4_i (dataFromRxFifo[3]), .DataFromRxFifo5_i (dataFromRxFifo[4]), .DataFromRxFifo6_i (dataFromRxFifo[5]), .DataFromRxFifo7_i (dataFromRxFifo[6]), .AnsData_o (muxedData) ); BUFG BUFG_inst ( .O(gclk), // 1-bit output: Clock output .I(Clk123_i) // 1-bit input: Clock input ); SmcRx SmcRx ( .Clk_i (gclk), .Rst_i (initRst), .SmcD_i (SmcData_i), .SmcA_i (SmcAddr_i), .SmcAwe_i (SmcAwe_i), .SmcAmsN_i (SmcAmsN_i), .SmcAoe_i (SmcAoe_i), .SmcAre_i (SmcAre_i), .SmcBe_i (SmcBe_i), .AnsData_i (muxedData), .Data_o (smcData), .Addr_o (smcAddr), .Val_o (smcVal) ); SmcDataMux SmcDataMuxer ( .Clk_i (gclk), .Rst_i (initRst), .SmcVal_i (smcVal), .SmcData_i (smcData), .SmcAddr_i (smcAddr), .ToRegMapVal_o (toRegMapVal), .ToRegMapData_o (toRegMapData), .ToRegMapAddr_o (toRegMapAddr), .ToFifoVal_o (toFifoVal), .ToFifoData_o (toFifoData) ); RegMap #( .CmdRegWidth(32), .AddrRegWidth(12) ) RegMap_inst ( .Clk_i(gclk), .Rst_i(initRst), .Data_i(toRegMapData), .Addr_i(toRegMapAddr), .Val_i(toRegMapVal), .SmcBe_i(SmcBe_i), .Led_o(Led_o), .AnsDataReg_o(ansData), //Spi0 .Spi0CtrlReg_o(spi0Ctrl), .Spi0ClkReg_o(spi0Clk), .Spi0CsDelayReg_o(spi0CsDelay), .Spi0CsCtrlReg_o(spi0CsCtrl), .Spi0TxFifoCtrlReg_o(spi0TxFifoCtrl), .Spi0RxFifoCtrlReg_o(spi0RxFifoCtrl), .Spi0TxFifoReg_o(spi0TxFifo), .Spi0RxFifoReg_o(spi0RxFifo), //Spi1 .Spi1CtrlReg_o(spi1Ctrl), .Spi1ClkReg_o(spi1Clk), .Spi1CsDelayReg_o(spi1CsDelay), .Spi1CsCtrlReg_o(spi1CsCtrl), .Spi1TxFifoCtrlReg_o(spi1TxFifoCtrl), .Spi1RxFifoCtrlReg_o(spi1RxFifoCtrl), .Spi1TxFifoReg_o(spi1TxFifo), .Spi1RxFifoReg_o(spi1RxFifo), //Spi2 .Spi2CtrlReg_o(spi2Ctrl), .Spi2ClkReg_o(spi2Clk), .Spi2CsDelayReg_o(spi2CsDelay), .Spi2CsCtrlReg_o(spi2CsCtrl), .Spi2TxFifoCtrlReg_o(spi2TxFifoCtrl), .Spi2RxFifoCtrlReg_o(spi2RxFifoCtrl), .Spi2TxFifoReg_o(spi2TxFifo), .Spi2RxFifoReg_o(Spi2RxFifo), //Spi3 .Spi3CtrlReg_o(spi3Ctrl), .Spi3ClkReg_o(spi3Clk), .Spi3CsDelayReg_o(spi3CsDelay), .Spi3CsCtrlReg_o(spi3CsCtrl), .Spi3TxFifoCtrlReg_o(spi3TxFifoCtrl), .Spi3RxFifoCtrlReg_o(spi3RxFifoCtrl), .Spi3TxFifoReg_o(Spi3TxFifo), .Spi3RxFifoReg_o(Spi3RxFifo), //Spi4 .Spi4CtrlReg_o(spi4Ctrl), .Spi4ClkReg_o(spi4Clk), .Spi4CsDelayReg_o(spi4CsDelay), .Spi4CsCtrlReg_o(spi4CsCtrl), .Spi4TxFifoCtrlReg_o(spi4TxFifoCtrl), .Spi4RxFifoCtrlReg_o(spi4RxFifoCtrl), .Spi4TxFifoReg_o(Spi4TxFifo), .Spi4RxFifoReg_o(Spi4RxFifo), //Spi5 .Spi5CtrlReg_o(spi5Ctrl), .Spi5ClkReg_o(spi5Clk), .Spi5CsDelayReg_o(spi5CsDelay), .Spi5CsCtrlReg_o(spi5CsCtrl), .Spi5TxFifoCtrlReg_o(spi5TxFifoCtrl), .Spi5RxFifoCtrlReg_o(spi5RxFifoCtrl), .Spi5TxFifoReg_o(Spi5TxFifo), .Spi5RxFifoReg_o(Spi5RxFifo), //Spi6 .Spi6CtrlReg_o(spi6Ctrl), .Spi6ClkReg_o(spi6Clk), .Spi6CsDelayReg_o(spi6CsDelay), .Spi6CsCtrlReg_o(spi6CsCtrl), .Spi6TxFifoCtrlReg_o(spi6TxFifoCtrl), .Spi6RxFifoCtrlReg_o(spi6RxFifoCtrl), .Spi6TxFifoReg_o(Spi6TxFifo), .Spi6RxFifoReg_o(Spi6RxFifo), .SpiTxRxEnReg_o(SpiTxRxEn), .GPIOAReg_o(GPIOA) ); MmcmWrapper MainMmcm ( .Clk_i (gclk), .Rst_i (initRst), .BaudRate0_i(baudRate[0]), .BaudRate1_i(baudRate[1]), .BaudRate2_i(baudRate[2]), .BaudRate3_i(baudRate[3]), .BaudRate4_i(baudRate[4]), .BaudRate5_i(baudRate[5]), .BaudRate6_i(baudRate[6]), .SpiClk_o (spiClkBus), .Clk100_o (Clk100_o), .Clk40_o (Clk40_o) ); genvar i; generate for (i = 0; i < SpiNum; i = i + 1) begin: SpiGen // RstSync SpiRstSync // ( // .Clk_i (spiClkBus[i]), // .Rst_i (initRst), // .Rst_o (spiSyncRst[i]) // ); DataFifoWrapper DataFifoWrapper ( .WrClk_i (gclk), .RdClk_i (Clk40_o), // .Rst_i (spiSyncRst[i] | FifoRxRst[i]), .FifoRxRst_i (fifoRxRst[i]), .FifoTxRst_i (fifoTxRst[i]), .SmcAre_i (SmcAre_i), .SmcAwe_i (SmcAwe_i), .ToFifoVal_i (toFifoVal[i]), .ToFifoRxData_i (dataToRxFifo[i]), .ToFifoRxWriteVal_i (valToRxFifo[i]), .ToFifoTxReadVal_i (valToTxFifoRead[i]), .ToFifoData_i (toFifoData[32*i+:32]), .ToSpiVal_o (toSpiVal[i]), .DataFromRxFifo_o (dataFromRxFifo[i]), .ToSpiData_o (toSpiData[i]) ); SPIm SPIm_inst ( .Clk_i(Clk40_o), .Start_i(ten[i]), .Rst_i(initRst| spiMode[i]), .SPIdata(toSpiData[i]), .Sck_o(SckR[i]), .Ss_o(SsR[i]), .Mosi0_o(Mosi0R[i]), .WidthSel_i(widthSel[i]), .PulsePol_i(CPOL[i]), .CPHA_i(CPHA[i]), .EndianSel_i(endianSel[i]), .LAG_i(lag[i]), .LEAD_i(leadx[i]), .Stop_i(stopDelay[i]), .SELST_i(selSt[i]), .Val_o(valToTxR[i]) ); SPIs SPIs_inst ( .Clk_i(Clk40_o), .Rst_i(initRst|SpiRst_o[i]| spiMode[i]), .Sck_i(SckR[i]), .Ss_i(SsR[i]), .Mosi0_i(Mosi0R[i]), .WidthSel_i(widthSel[i]), .SELST_i(selSt[i]), .DataToRxFifo_o(dataToRxFifoR[i]), .Val_o(valToRxR[i]) ); QuadSPIm QuadSPIm_inst ( .Clk_i(Clk40_o), .Start_i(ten[i]), .Rst_i(initRst| !spiMode[i]), .SpiDataVal_i (toSpiVal), // .SPIdata(32'h2aaa00aa), .SPIdata(toSpiData[i]), .Sck_o(SckQ[i]), .Ss_o(SsQ[i]), .Mosi0_i(Mosi0Q[i]), .Mosi1_i(Mosi1[i]), .Mosi2_i(Mosi2[i]), .Mosi3_i(Mosi3[i]), .WidthSel_i(widthSel[i]), .PulsePol_i(CPOL[i]), .CPHA_i(CPHA[i]), .EndianSel_i(endianSel[i]), .LAG_i(lag[i]), .LEAD_i(leadx[i]), .Stop_i(stopDelay[i]), .SELST_i(selSt[i]), .Val_o(valToTxQ[i]) ); QuadSPIs QuadSPIs_inst ( .Clk_i(Clk40_o), .Rst_i(initRst|SpiRst_o[i]| !spiMode[i]), .Sck_i(SckQ[i]), .Ss_i(SsQ[i]), .Mosi0_i(Mosi0Q[i]), .Mosi1_i(Mosi1[i]), .Mosi2_i(Mosi2[i]), .Mosi3_i(Mosi3[i]), .WidthSel_i(widthSel[i]), .SELST_i(selSt[i]), .DataToRxFifo_o(dataToRxFifoQ[i]), .Val_o(valToRxQ[i]) ); end endgenerate InitRst InitRst_inst ( .clk_i(gclk), .signal_o(initRst) ); endmodule