xilinx.com xci unknown 1.0 DataFifo 100000000 0 0 0.0 100000000 0 0 0.0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0.0 100000000 0 0 0.0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 100000000 0 0 0 0 0 undef 0.0 0 0 0 0 100000000 0 0 0.0 0 0 0 0 0 0 0 8 1 1 1 1 4 0 32 1 1 1 64 1 8 1 1 1 1 0 0 9 BlankString 32 1 32 64 1 64 2 0 32 0 1 0 0 0 0 0 0 0 0 spartan7 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 1 1 1 1 0 0 1 BlankString 1 0 0 0 1 0 512x36 1kx18 512x36 1kx36 512x36 1kx36 512x36 2 1022 1022 1022 1022 1022 1022 3 0 0 0 0 0 0 0 509 1023 1023 1023 1023 1023 1023 508 0 0 0 0 0 0 0 0 0 9 512 1 9 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 512 1024 16 1024 16 1024 16 1 9 10 4 10 4 10 4 1 32 0 0 false false false 0 0 Slave_Interface_Clock_Enable Common_Clock DataFifo 64 false 9 false false 0 2 1022 1022 1022 1022 1022 1022 3 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Independent_Clocks_Block_RAM 0 509 1023 1023 1023 1023 1023 1023 508 false false false 0 Native false false false false false false false false false false false false false false 32 512 1024 16 1024 16 1024 16 false 32 512 Embedded_Reg false false Active_High Active_High AXI4 Standard_FIFO No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 1 false 9 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered false Asynchronous_Reset false 1 0 0 1 1 4 false false Active_High Active_High false false false false false Active_High 0 false Active_High 1 false 9 false FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO spartan7 xc7s25 csga225 VERILOG MIXED -2 TRUE TRUE IP_Flow 7 TRUE ../../../../S5443SRAM.gen/sources_1/ip/DataFifo . 2022.1 OUT_OF_CONTEXT