module RstSync 
(
    input	Clk_i,
    input	Rst_i,

	output	Rst_o
);
//================================================================================
//	REG/WIRE
//================================================================================
	reg	rstReg0;
	reg	rstReg1;
//================================================================================
//	ASSIGNMENTS
//================================================================================
	assign	Rst_o	=	rstReg1;
//================================================================================
//	LOCALPARAMS
//================================================================================

//================================================================================
//	CODING
//================================================================================

always	@(posedge	Clk_i)	begin
	rstReg0	<=	Rst_i;
	rstReg1	<=	rstReg0;
end
endmodule