xilinx.com xci unknown 1.0 ClkDiv false 100000000 false 100000000 false 100000000 false 100000000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 1 LEVEL_HIGH 100000000 0 0 0.000 0 0 100000000 0 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 0 MMCM cddcdone cddcreq 0000 0000 clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 81.30000000000001 100.0 0000 0000 12.00126 0000 0000 79.60833 BUFG 50.0 false 12.00126 0.000 50.000 12 0.000 1 0000 0000 70.24265 BUFG 50.0 false 79.60833 0.000 50.000 80.000 0.000 1 1 0000 0000 59.70625 BUFG 50.0 false 70.24265 0.000 50.000 70.000 0.000 1 1 0000 0000 49.75521 BUFG 50.0 false 59.70625 0.000 50.000 60.000 0.000 1 1 0000 0000 39.80417 BUFG 50.0 false 49.75521 0.000 50.000 50.000 0.000 1 1 0000 0000 29.85312 BUFG 50.0 false 39.80417 0.000 50.000 40.000 0.000 1 1 BUFG 50.0 false 29.85312 0.000 50.000 30 0.000 1 1 VCO clk_in_sel clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 CLK_VALID NA daddr dclk den din 0000 1 0.15 0.17142857142857143 0.2 0.24 0.3 0.4 dout drdy dwe 93.000 1.000 0 0 0 0 0 0 0 0 FDBK_AUTO 0000 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_________123.000____________0.010 no_secondary_input_clock input_clk_stopped 0 Units_MHz No_Jitter locked 0000 0000 0000 false false false false false false false false OPTIMIZED 29.125 0.000 FALSE 8.130 10.000 99.500 0.500 0.000 FALSE 15 0.500 0.000 FALSE 17 0.500 0.000 FALSE 20 0.500 0.000 FALSE FALSE 24 0.500 0.000 FALSE 30 0.500 0.000 FALSE 40 0.500 0.000 FALSE FALSE ZHOLD 3 None 0.010 0.010 FALSE 64.000 2.000 7 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) clk_out1__12.00126______0.000______50.0______241.413____165.815 clk_out2__79.60833______0.000______50.0______153.004____165.815 clk_out3__70.24265______0.000______50.0______156.812____165.815 clk_out4__59.70625______0.000______50.0______162.012____165.815 clk_out5__49.75521______0.000______50.0______168.233____165.815 clk_out6__39.80417______0.000______50.0______176.499____165.815 clk_out7__29.85312______0.000______50.0______188.450____165.815 0 0 128.000 1.000 WAVEFORM UNKNOWN false false false false false OPTIMIZED 1 0.000 1.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 No notes 0.010 power_down 0000 1 clk_in1 MMCM AUTO 123.000 0.010 10.000 Single_ended_clock_capable_pin psclk psdone psen psincdec 100.0 0 reset 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 4000 0.004 STATUS 11 32 100.0 100.0 100.0 100.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1440.000 600.000 ClkDiv MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 81.30000000000001 0.010 100.0 0.010 BUFG 241.413 false 165.815 50.000 12 0.000 1 true BUFG 153.004 false 165.815 50.000 80.000 0.000 1 true BUFG 156.812 false 165.815 50.000 70.000 0.000 1 true BUFG 162.012 false 165.815 50.000 60.000 0.000 1 true BUFG 168.233 false 165.815 50.000 50.000 0.000 1 true BUFG 176.499 false 165.815 50.000 40.000 0.000 1 true BUFG 188.450 false 165.815 50.000 30 0.000 1 true 600.000 Custom Custom clk_in_sel clk_out1 false clk_out2 false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto ClkDiv daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 29.125 0.000 false 8.130 10.000 99.500 0.500 0.000 false 15 0.500 0.000 false 17 0.500 0.000 false 20 0.500 0.000 false false 24 0.500 0.000 false 30 0.500 0.000 false 40 0.500 0.000 false false ZHOLD 3 None 0.010 0.010 false 7 false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 clk_in1 MMCM mmcm_adv 123.000 0.010 10.000 Single_ended_clock_capable_pin psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false true false false false true false true false false false spartan7 xc7s25 csga225 VERILOG MIXED -2 TRUE TRUE IP_Flow 6 TRUE ../../../../S5443_3.gen/sources_1/ip/ClkDiv . 2020.2 OUT_OF_CONTEXT