module DataOutMux#( parameter CmdRegWidth = 32, parameter AddrRegWidth= 12 ) ( input Rst_i, input Clk_i, input SmcAre_i, input [AddrRegWidth-1:0] Addr_i, input [AddrRegWidth-1:0] ToRegMapAddr_i, input [CmdRegWidth/2-1:0] DataFromRegMap_i, input [CmdRegWidth-1:0] DataFromRxFifo1_i, input [CmdRegWidth-1:0] DataFromRxFifo2_i, input [CmdRegWidth-1:0] DataFromRxFifo3_i, input [CmdRegWidth-1:0] DataFromRxFifo4_i, input [CmdRegWidth-1:0] DataFromRxFifo5_i, input [CmdRegWidth-1:0] DataFromRxFifo6_i, input [CmdRegWidth-1:0] DataFromRxFifo7_i, output [CmdRegWidth/2-1:0] AnsData_o ); wire [0:31] dataFromRxFifo [6:0]; wire [15:0] dataFromRegMap; reg [15:0] dataFromRxFifoR; (* dont_touch = "true" *)reg [CmdRegWidth/2-1:0] dataFromRxFifoR1; reg [CmdRegWidth-1:0] dataFromRxFifoR2; reg [CmdRegWidth-1:0] dataFromRxFifoR3; reg [CmdRegWidth-1:0] dataFromRxFifoR4; reg [CmdRegWidth-1:0] dataFromRxFifoR5; reg [CmdRegWidth-1:0] dataFromRxFifoR6; reg [CmdRegWidth-1:0] dataFromRxFifoR7; assign dataFromRxFifo[0] = DataFromRxFifo1_i; assign dataFromRxFifo[1] = DataFromRxFifo2_i; assign dataFromRxFifo[2] = DataFromRxFifo3_i; assign dataFromRxFifo[3] = DataFromRxFifo4_i; assign dataFromRxFifo[4] = DataFromRxFifo5_i; assign dataFromRxFifo[5] = DataFromRxFifo6_i; assign dataFromRxFifo[6] = DataFromRxFifo7_i; assign dataFromRegMap = DataFromRegMap_i; assign AnsData_o = (ToRegMapAddr_i)?dataFromRegMap:dataFromRxFifoR; always @(*) begin if (Rst_i) begin dataFromRxFifoR1 = 0; dataFromRxFifoR2 = 0; dataFromRxFifoR3 = 0; dataFromRxFifoR4 = 0; dataFromRxFifoR5 = 0; dataFromRxFifoR6 = 0; dataFromRxFifoR7 = 0; end else begin if (!SmcAre_i) begin case(Addr_i) 12'h1c : begin dataFromRxFifoR1 = DataFromRxFifo1_i[31:16]; end 12'h6c : begin dataFromRxFifoR2 = DataFromRxFifo2_i; end 12'h10c : begin dataFromRxFifoR3 = DataFromRxFifo3_i; end 12'h15c : begin dataFromRxFifoR4 = DataFromRxFifo4_i; end 12'h1ac : begin dataFromRxFifoR5 = DataFromRxFifo5_i; end 12'h1fc : begin dataFromRxFifoR6 = DataFromRxFifo6_i; end 12'h24c : begin dataFromRxFifoR7 = DataFromRxFifo7_i; end endcase end end end always @(*) begin case (Addr_i) 12'h1c: begin dataFromRxFifoR = DataFromRxFifo1_i[15:0]; end 12'h1e: begin dataFromRxFifoR = dataFromRxFifoR1; end 12'h6c: begin dataFromRxFifoR = DataFromRxFifo2_i[15:0]; end 12'h6e: begin dataFromRxFifoR = dataFromRxFifoR2[31:16]; end 12'h10c: begin dataFromRxFifoR = DataFromRxFifo3_i[15:0]; end 12'h10e: begin dataFromRxFifoR = dataFromRxFifoR3[31:16]; end 12'h15c: begin dataFromRxFifoR = DataFromRxFifo4_i[15:0]; end 12'h15e: begin dataFromRxFifoR = dataFromRxFifoR4[31:16]; end 12'h1ac: begin dataFromRxFifoR = DataFromRxFifo5_i[15:0]; end 12'h1ae: begin dataFromRxFifoR = dataFromRxFifoR5[31:16]; end 12'h1fc: begin dataFromRxFifoR = DataFromRxFifo6_i[15:0]; end 12'h1fe: begin dataFromRxFifoR = dataFromRxFifoR6[31:16]; end 12'h24c: begin dataFromRxFifoR = DataFromRxFifo7_i[15:0]; end 12'h24e: begin dataFromRxFifoR = dataFromRxFifoR7[31:16]; end default: begin dataFromRxFifoR = 16'h0; end endcase end endmodule