xilinx.com xci unknown 1.0 ClkDiv false 100000000 false 100000000 false 100000000 false 100000000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 1 LEVEL_HIGH 100000000 0 0 0.000 0 0 100000000 0 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 0 MMCM cddcdone cddcreq 0000 0000 clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 81.30000000000001 100.0 0000 0000 99.93750 0000 0000 79.95000 BUFG 50.0 false 99.93750 0.000 50.000 100.000 0.000 1 0000 0000 70.54412 BUFG 50.0 false 79.95000 0.000 50.000 80.000 0.000 1 1 0000 0000 59.96250 BUFG 50.0 false 70.54412 0.000 50.000 70.000 0.000 1 1 0000 0000 49.96875 BUFG 50.0 false 59.96250 0.000 50.000 60.000 0.000 1 1 0000 0000 39.97500 BUFG 50.0 false 49.96875 0.000 50.000 50.000 0.000 1 1 0000 0000 26.65000 BUFG 50.0 false 39.97500 0.000 50.000 40.000 0.000 1 1 BUFG 50.0 false 26.65000 0.000 50.000 26.666 0.000 1 1 VCO clk_in_sel clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 CLK_VALID NA daddr dclk den din 0000 1 1.25 1.4285714285714286 1.6666666666666667 2.0 2.5 3.7500937523438087 dout drdy dwe 93.000 1.000 0 0 0 0 0 0 0 0 FDBK_AUTO 0000 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_________123.000____________0.010 no_secondary_input_clock input_clk_stopped 0 Units_MHz No_Jitter locked 0000 0000 0000 false false false false false false false false OPTIMIZED 9.750 0.000 FALSE 8.130 10.000 12.000 0.500 0.000 FALSE 15 0.500 0.000 FALSE 17 0.500 0.000 FALSE 20 0.500 0.000 FALSE FALSE 24 0.500 0.000 FALSE 30 0.500 0.000 FALSE 45 0.500 0.000 FALSE FALSE ZHOLD 1 None 0.010 0.010 FALSE 64.000 2.000 7 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) clk_out1__99.93750______0.000______50.0______112.035_____85.478 clk_out2__79.95000______0.000______50.0______116.822_____85.478 clk_out3__70.54412______0.000______50.0______119.640_____85.478 clk_out4__59.96250______0.000______50.0______123.604_____85.478 clk_out5__49.96875______0.000______50.0______128.250_____85.478 clk_out6__39.97500______0.000______50.0______134.251_____85.478 clk_out7__26.65000______0.000______50.0______146.187_____85.478 0 0 128.000 1.000 WAVEFORM UNKNOWN false false false false false OPTIMIZED 1 0.000 1.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 No notes 0.010 power_down 0000 1 clk_in1 MMCM AUTO 123.000 0.010 10.000 Single_ended_clock_capable_pin psclk psdone psen psincdec 100.0 0 reset 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 4000 0.004 STATUS 11 32 100.0 100.0 100.0 100.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1440.000 600.000 ClkDiv MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 81.30000000000001 0.010 100.0 0.010 BUFG 112.035 false 85.478 50.000 100.000 0.000 1 true BUFG 116.822 false 85.478 50.000 80.000 0.000 1 true BUFG 119.640 false 85.478 50.000 70.000 0.000 1 true BUFG 123.604 false 85.478 50.000 60.000 0.000 1 true BUFG 128.250 false 85.478 50.000 50.000 0.000 1 true BUFG 134.251 false 85.478 50.000 40.000 0.000 1 true BUFG 146.187 false 85.478 50.000 26.666 0.000 1 true 600.000 Custom Custom clk_in_sel clk_out1 false clk_out2 false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto ClkDiv daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 9.750 0.000 false 8.130 10.000 12.000 0.500 0.000 false 15 0.500 0.000 false 17 0.500 0.000 false 20 0.500 0.000 false false 24 0.500 0.000 false 30 0.500 0.000 false 45 0.500 0.000 false false ZHOLD 1 None 0.010 0.010 false 7 false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 clk_in1 MMCM mmcm_adv 123.000 0.010 10.000 Single_ended_clock_capable_pin psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false true false false false true false true false false false spartan7 xc7s25 csga225 VERILOG MIXED -2 TRUE TRUE IP_Flow 6 TRUE ../../../../S5443_3.gen/sources_1/ip/ClkDiv . 2020.2 OUT_OF_CONTEXT