`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 10.10.2018 01:07:38
// Design Name: 
// Module Name: sram_ctrl2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module	SmcRx
#(
	parameter	DataInOutWidth	=	16,
	parameter	AddrWidth		=	12
)
(
	input	Clk_i,                       
	input	Rst_i,                         

	inout	[DataInOutWidth-1:0]	SmcD_i,
	input	[AddrWidth-2:0]	SmcA_i,
	input	SmcAwe_i,
	input	SmcAmsN_i,
	input	SmcAoe_i,
	input	SmcAre_i,	
	input	[1:0]	SmcBe_i,	
	
	input	[DataInOutWidth-1:0]	AnsData_i,
	
	output	[1:0]	Be_o,
	output	[DataInOutWidth-1:0]	Data_o,
	output	[AddrWidth-1:0]	Addr_o,
	output	Val_o
);

//================================================================================
//  REG/WIRE
	
	
	reg	[DataInOutWidth-1:0]	inDataReg;
	reg	[AddrWidth-1:0]			addrReg;
	reg	valReg;
	
	reg	[DataInOutWidth-1:0]	outDataReg;
	reg	[1:0]	beReg;
//================================================================================
//  LOCALPARAM

//================================================================================
//  ASSIGNMENTS	
	assign	Data_o	=	inDataReg;
	assign	Addr_o	=	addrReg;
	assign	Val_o	=	valReg;
	assign	Be_o	=	beReg;
	
	assign	SmcD_i	=	(!SmcAoe_i && !SmcAre_i)?	AnsData_i:16'bz;
//================================================================================
//  CODING
	
always	@(posedge	Clk_i)	begin
	if	(!Rst_i)	begin
		if	(!SmcAmsN_i)	begin
			if	(!SmcAwe_i)	begin
				addrReg	<=	{SmcA_i,1'b0};
				inDataReg	<=	SmcD_i;
				valReg	<=	1'b1;
				beReg	<=	SmcBe_i;
			end	else	begin
				valReg	<=	0;
			end
			
			if	(!SmcAoe_i)	begin
				addrReg		<=	{SmcA_i,1'b0};
				outDataReg	<=	AnsData_i;
			end	
		end
		else	begin
			valReg	<=	0;
		end
	end	else	begin
		inDataReg	<=	0;
		outDataReg	<=	0;
		addrReg	<=	0;
		valReg		<=	0;
		beReg	<=	2'b0;
	end
end

endmodule