`timescale 1ns / 1ps
module S5443_3_tb;

parameter CLK_PERIOD = 8.13; // Clock period in ns




reg Clk_i;
reg Rst_i;
reg [10:0] SmcAddr_i;
reg [15:0]SmcData_i;
reg SmcAre_i;
reg SmcAwe_i;
wire SmcAmsN_i;
wire [1:0] SmcBe_i;
reg SmcAoe_i;

reg [31:0] tb_cnt;

wire [15:0] smcData;

assign SmcBe_i = (tb_cnt >0 && tb_cnt <=44) ? 2'b00 : 2'b11;
assign SmcAmsN_i = (tb_cnt > 0 && tb_cnt <= 44) ? 1'b0 : 1'b1;
assign smcData = SmcData_i;

always #(CLK_PERIOD/2) Clk_i = ~Clk_i;


    S5443_3Top uut (
        .Clk123_i(Clk_i), 
        .SmcAddr_i(SmcAddr_i), 
        .SmcData_i(smcData), 
        .SmcAwe_i(SmcAwe_i), 
        .SmcAmsN_i(SmcAmsN_i), 
        .SmcAre_i(SmcAre_i), 
        .SmcBe_i(SmcBe_i), 
        .SmcAoe_i(SmcAoe_i), 
        .Ld_i(Ld_i), 
        .Led_o(), 
        .Mosi0_o(), 
        .Mosi1_io(), 
        .Mosi2_o(), 
        .Mosi3_o(), 
        .Ss_o(), 
        .SsFlash_o(), 
        .Sck_o(), 
        .SpiRst_o(), 
        .LD_o()
    );




always @(posedge Clk_i) begin 
    if (Rst_i) begin
        SmcAwe_i <= 1'b1;
    end
    else begin 
        case (tb_cnt)
        0: begin 
            SmcAwe_i <= 1'b1;
        end 
        1: begin 
            SmcAwe_i <= 1'b1;
        end
        2: begin 
            SmcAwe_i <= 1'b1;
        end
        3: begin 
            SmcAwe_i <= 1'b0;
        end
        4: begin 
            SmcAwe_i <= 1'b0;
        end
        5: begin 
            SmcAwe_i <= 1'b0;
        end
        6: begin 
            SmcAwe_i <= 1'b1;
        end
        7: begin 
            SmcAwe_i <= 1'b0;
        end
        8: begin 
            SmcAwe_i <= 1'b1;
        end
        9: begin 
            SmcAwe_i <= 1'b0;
        end
        10: begin 
            SmcAwe_i <= 1'b1;
        end
        11: begin 
            SmcAwe_i <= 1'b0;
        end
        12: begin 
            SmcAwe_i <= 1'b1;
        end
        13: begin 
            SmcAwe_i <= 1'b0;
        end
        14: begin 
            SmcAwe_i <= 1'b1;
        end
        15: begin 
            SmcAwe_i <= 1'b0;
        end
        16: begin 
            SmcAwe_i <= 1'b1;
        end
        17: begin 
            SmcAwe_i <= 1'b0;
        end
        18: begin 
            SmcAwe_i <= 1'b1;
        end
        19: begin 
            SmcAwe_i <= 1'b0;
        end
        20: begin 
            SmcAwe_i <= 1'b1;
        end
        21: begin 
            SmcAwe_i <= 1'b0;
        end
        22: begin 
            SmcAwe_i <= 1'b1;
        end
        23: begin 
            SmcAwe_i <= 1'b0;
        end
        24: begin 
            SmcAwe_i <= 1'b1;
        end
        25: begin 
            SmcAwe_i <= 1'b0;
        end
        26: begin 
            SmcAwe_i <= 1'b1;
        end
        27: begin 
            SmcAwe_i <= 1'b0;
        end
        28: begin 
            SmcAwe_i <= 1'b1;
        end
        29: begin 
            SmcAwe_i <= 1'b0;
        end
        30: begin 
            SmcAwe_i <= 1'b1;
        end
        31: begin 
            SmcAwe_i <= 1'b0;
        end
        32: begin 
            SmcAwe_i <= 1'b1;
        end
        33: begin 
            SmcAwe_i <= 1'b0;
        end
        34: begin 
            SmcAwe_i <= 1'b1;
        end
        35: begin 
            SmcAwe_i <= 1'b0;
        end
        36: begin 
            SmcAwe_i <= 1'b1;
        end
        37: begin 
            SmcAwe_i <= 1'b0;
        end
        38: begin 
            SmcAwe_i <= 1'b1;
        end
        39: begin 
            SmcAwe_i <= 1'b0;
        end
        40: begin 
            SmcAwe_i <= 1'b1;
        end
        41: begin 
            SmcAwe_i <= 1'b0;
        end
        42: begin 
            SmcAwe_i <= 1'b1;
        end
        43: begin 
            SmcAwe_i <= 1'b0;
        end
        44: begin 
            SmcAwe_i <= 1'b1;
        end
    endcase
    end
end




always @(posedge Clk_i) begin 
    if (Rst_i) begin 
        SmcAddr_i <= 0;
        SmcData_i <= 0;
    end
    else begin
        case (tb_cnt)
        0: begin 
            SmcAddr_i <= 12'h00f;
            SmcData_i <= 16'h0000;
        end
        2: begin 
            SmcAddr_i <= 12'h7fc;
            SmcData_i <= 16'h0001;
        end
        4: begin 
            SmcAddr_i <= 12'h7fd;
            SmcData_i <= 16'h0000;
        end
        6: begin 
            SmcAddr_i <= 12'h7fe;
            SmcAddr_i <= 16'h0000;
        end
        8: begin 
            SmcAddr_i <= 12'h0;
            SmcData_i <= 16'h7f;
        end
        10: begin 
            SmcAddr_i <= 12'h1;
            SmcData_i <= 16'h0;
        end
        12: begin 
             SmcAddr_i <= 12'h2;
             SmcData_i <= 16'hc;
        end
        14: begin 
            SmcAddr_i <= 12'h3;
            SmcData_i <= 16'h0;
        end
        16: begin 
            SmcAddr_i <= 12'h4;
            SmcData_i <= 16'hc;
        end
        18: begin 
            SmcAddr_i <= 12'h5;
            SmcData_i <= 16'h0;
        end
        20: begin 
             SmcAddr_i <= 12'h6;
             SmcData_i <= 16'h3;
        end
        22:  begin 
            SmcAddr_i <= 12'h7;
            SmcData_i <= 16'h0;
        end
        24: begin
             SmcAddr_i <= 12'h8;
             SmcData_i <= 16'h1;
        end
        26: begin 
            SmcAddr_i <= 12'h9;
            SmcData_i <= 16'h0;
        end
        28: begin 
             SmcAddr_i <= 12'ha;
             SmcData_i <= 16'h1;
        end
        30: begin 
             SmcAddr_i <= 12'hb;
             SmcData_i <= 16'h0;
        end
        32: begin 
             SmcAddr_i <= 12'h780;
             SmcData_i <= 16'h1;
        end
        34: begin
             SmcAddr_i <= 12'h781;
             SmcData_i <= 16'h0;
        end
        36: begin
             SmcAddr_i <= 12'h7f8;
             SmcData_i <= 16'h0;
        end
        38: begin 
             SmcAddr_i <= 12'h7f9;
             SmcData_i <= 16'h0;
        end
        40: begin 
            SmcAddr_i <= 12'h00c;
            SmcData_i <= 16'h1;
        end
        42: begin 
            SmcAddr_i <= 12'h00d;
            SmcData_i <= 16'h0;
        end
    endcase
    end
end



always @(posedge Clk_i) begin 
    if (Rst_i) begin 
        tb_cnt <= 0;
    end
    else begin 
        tb_cnt <= tb_cnt + 1;
    end
end


// always @(*) begin 
//     txNextState = IDLE;
//     case(txCurrState)
//     IDLE : begin 
//             if (txWork) begin 
//                 txNextState = CMD;
//             end
//             else begin 
//                 txNextState = IDLE;
//             end
//         end
//     WRITE : begin 
//             if () begin 
//                 txNextState = WRITE;
//             end
//             else begin 
//                 txNextState = IDLE;
//             end
//         end


initial begin 
    Clk_i = 1'b0;
    Rst_i = 1'b1;
    SmcAre_i = 1'b1;
    SmcAoe_i = 1'b1;
    #(CLK_PERIOD*10) Rst_i = 1'b0;




end

endmodule