`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 10.10.2018 01:07:38
// Design Name: 
// Module Name: sram_ctrl2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module	MasterFpgaTopTb
(
	input	Clk_i
);

//================================================================================
//  REG/WIRE
	reg	clk120Dsp;
	reg	clk120Fpga;
	reg	start;
	reg	rstN;
	reg	ForceRstN;
	
	wire	[15:0]	data;
	wire	[24:0]	addr;
	wire	awe;
	wire	amsn;
	wire	aoe;
	wire	are;
	wire	[1:0]	be;
//================================================================================
//  LOCALPARAM
	
//================================================================================
//  ASSIGNMENTS	
	always	#4.2	clk120Dsp	=	~clk120Dsp;
	always	#4.2	clk120Fpga	=	~clk120Fpga;
//================================================================================
//  CODING

initial	begin
	rstN		=	0;
	ForceRstN	=	0;
	clk120Dsp	=	1;
	start		=	0;
	clk120Fpga	=	0;
	#20
	rstN		=	1;
	ForceRstN	=	1;
	#100
	start	=	1;
	#4.2
	start	=	0;
	
end

DspSramModel	DspSramInterface
(
	.Clk120MHz_i	(clk120Dsp),
	.RstN_i			(rstN),
	.SmcD_o			(data),
	.SmcA_o			(addr),
	.SmcAwe_o		(awe),
	.SmcAmsN_o		(amsn),
	.SmcAoe_o		(aoe),
	.SmcAre_o		(are),
	.SmcBe_o		(be),
	
	.Start_i		(start)
);

MasterFpgaTop	MasterFpgaTop
(
	.Clk_i		(clk120Fpga),
	.RstN_i		(rstN),
	.ForceRstN_i(ForceRstN),

	.SmcD_i		(data),
	.SmcA_i		(addr),
	.SmcAwe_i	(awe),
	.SmcAmsN_i	(amsn),
	.SmcAoe_i	(aoe),
	.SmcAre_i	(are),
	.SmcBe_i	(be),
	
	.Data_o		(),
	.Addr_o		(),
	.Val_o		()
);
endmodule