`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 10/30/2023 11:24:31 AM // Design Name: // Module Name: S5443_3Top // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module S5443_3Top #( parameter CmdRegWidth = 32, parameter AddrRegWidth = 12, parameter SpiNum = 7 )( input Clk123_i, input [AddrRegWidth-2:0] Addr_i, inout [CmdRegWidth/2-1:0] Data_i, input [SpiNum-1:0] SpiRst_i, input writeEn_i, input readEn_i, // input DspRst_i, input [1:0] BE_i, input outputEn_i, output Led_o, output [SpiNum-1:0] Mosi0_o, output [SpiNum-1:0] Mosi1_o, output [SpiNum-1:0] Mosi2_o, output [SpiNum-1:0] Mosi3_o, output [SpiNum-1:0] Ss_o, output [SpiNum-1:0] Sck_o ); //================================================================================ // REG/WIRE //================================================================================ wire Clk100_i; wire [SpiNum-1:0]Sck; wire [SpiNum-1:0] Ss; wire [SpiNum-1:0]Mosi0; wire [SpiNum-1:0]Mosi1; wire [SpiNum-1:0]Mosi2; wire [SpiNum-1:0]Mosi3; wire [SpiNum-1:0] ten; wire clk80; wire clk61; wire Rst_i; wire gclk; wire [15:0] baudRate [SpiNum-1:0]; wire [19:0] baudRateexp; //SPI0 wire [CmdRegWidth-1:0] Spi0Ctrl; wire [CmdRegWidth-1:0] Spi0Clk; wire [CmdRegWidth-1:0] Spi0CsDelay; wire [CmdRegWidth-1:0] Spi0CsCtrl; wire [CmdRegWidth-1:0] Spi0TxFifoCtrl; wire [CmdRegWidth-1:0] Spi0RxFifoCtrl; wire [CmdRegWidth-1:0] Spi0TxFifo; wire [CmdRegWidth-1:0] Spi0RxFifo; //SPI1 wire [CmdRegWidth-1:0] Spi1Ctrl; wire [CmdRegWidth-1:0] Spi1Clk; wire [CmdRegWidth-1:0] Spi1CsDelay; wire [CmdRegWidth-1:0] Spi1CsCtrl; wire [CmdRegWidth-1:0] Spi1TxFifoCtrl; wire [CmdRegWidth-1:0] Spi1RxFifoCtrl; wire [CmdRegWidth-1:0] Spi1TxFifo; wire [CmdRegWidth-1:0] Spi1RxFifo; //SPI2 wire [CmdRegWidth-1:0] Spi2Ctrl; wire [CmdRegWidth-1:0] Spi2Clk; wire [CmdRegWidth-1:0] Spi2CsDelay; wire [CmdRegWidth-1:0] Spi2CsCtrl; wire [CmdRegWidth-1:0] Spi2TxFifoCtrl; wire [CmdRegWidth-1:0] Spi2RxFifoCtrl; wire [CmdRegWidth-1:0] Spi2TxFifo; wire [CmdRegWidth-1:0] Spi2RxFifo; //SPI3 wire [CmdRegWidth-1:0] Spi3Ctrl; wire [CmdRegWidth-1:0] Spi3Clk; wire [CmdRegWidth-1:0] Spi3CsDelay; wire [CmdRegWidth-1:0] Spi3CsCtrl; wire [CmdRegWidth-1:0] Spi3TxFifoCtrl; wire [CmdRegWidth-1:0] Spi3RxFifoCtrl; wire [CmdRegWidth-1:0] Spi3TxFifo; wire [CmdRegWidth-1:0] Spi3RxFifo; //SPI4 wire [CmdRegWidth-1:0] Spi4Ctrl; wire [CmdRegWidth-1:0] Spi4Clk; wire [CmdRegWidth-1:0] Spi4CsDelay; wire [CmdRegWidth-1:0] Spi4CsCtrl; wire [CmdRegWidth-1:0] Spi4TxFifoCtrl; wire [CmdRegWidth-1:0] Spi4RxFifoCtrl; wire [CmdRegWidth-1:0] Spi4TxFifo; wire [CmdRegWidth-1:0] Spi4RxFifo; //SPI5 wire [CmdRegWidth-1:0] Spi5Ctrl; wire [CmdRegWidth-1:0] Spi5Clk; wire [CmdRegWidth-1:0] Spi5CsDelay; wire [CmdRegWidth-1:0] Spi5CsCtrl; wire [CmdRegWidth-1:0] Spi5TxFifoCtrl; wire [CmdRegWidth-1:0] Spi5RxFifoCtrl; wire [CmdRegWidth-1:0] Spi5TxFifo; wire [CmdRegWidth-1:0] Spi5RxFifo; //SPI6 wire [CmdRegWidth-1:0] Spi6Ctrl; wire [CmdRegWidth-1:0] Spi6Clk; wire [CmdRegWidth-1:0] Spi6CsDelay; wire [CmdRegWidth-1:0] Spi6CsCtrl; wire [CmdRegWidth-1:0] Spi6TxFifoCtrl; wire [CmdRegWidth-1:0] Spi6RxFifoCtrl; wire [CmdRegWidth-1:0] Spi6TxFifo; wire [CmdRegWidth-1:0] Spi6RxFifo; wire [CmdRegWidth-1:0] SpiTxRxEn; wire [CmdRegWidth-1:0] GPIOA; //================================================================================ // ASSIGNMENTS //================================================================================ assign addr = {Addr_i, 1'b0}; assign Data_i = (!outputEn_i) ? data : 16'bz; assign ten = SpiTxRxEn[6:0]; assign Mosi0_o = Mosi0; assign Mosi1_o = Mosi1; assign Mosi2_o = Mosi2; assign Mosi3_o = Mosi3; assign Ss_o = Ss; assign Sck_o = Sck; // assign baudRate[15:0][0] =Spi0Clk[15:0]; // assign baudRate[15:0][1] =Spi1Clk[15:0]; // assign baudRate[15:0][2] =Spi2Clk[15:0]; // assign baudRate[15:0][3] =Spi3Clk[15:0]; // assign baudRate[15:0][4] =Spi4Clk[15:0]; // assign baudRate[15:0][5] =Spi5Clk[15:0]; // assign baudRate[15:0][6] =Spi6Clk[15:0]; //================================================================================ // CODING //================================================================================ BUFG BUFG_inst ( .O(gclk), // 1-bit output: Clock output .I(Clk123_i) // 1-bit input: Clock input ); clk_wiz_0 ClkGen ( .s_axi_aclk (), // input s_axi_aclk .s_axi_aresetn (), // input s_axi_aresetn, .s_axi_awaddr (), // input [10 : 0] s_axi_awaddr, .s_axi_awvalid (), // input s_axi_awvalid, .s_axi_awready (), // output s_axi_awready, .s_axi_wdata (), // input [31 : 0] s_axi_wdata, .s_axi_wstrb (), // input [3 : 0] s_axi_wstrb, .s_axi_wvalid (), // input s_axi_wvalid, .s_axi_wready (), // output s_axi_wready, .s_axi_bresp (), // output [1 : 0] s_axi_bresp, .s_axi_bvalid (), // output s_axi_bvalid, .s_axi_bready (), // input s_axi_bready, .s_axi_araddr (), // input [10 : 0] s_axi_araddr, .s_axi_arvalid (), // input s_axi_arvalid, .s_axi_arready (), // output s_axi_arready, .s_axi_rdata (), // output [31 : 0] s_axi_rdata, .s_axi_rresp (), // output [1 : 0] s_axi_rresp, .s_axi_rvalid (), // output s_axi_rvalid, .s_axi_rready (), // input s_axi_rready, // Clock out ports .clk_out1(Clk100_i), // output clk_out1 // Status and control signals .locked(), // output locked // Clock in ports .clk_in1(gclk)); // input clk_in1 RegMap #( .CmdRegWidth(32), .AddrRegWidth(12) ) RegMap_inst ( .Clk_i(gclk), .Rst_i(Rst_i), .Data_i(Data_i), .Addr_i(addr), .wrEn_i(writeEn_i), .rdEn_i(readEn_i), .BE_i(BE_i), .Led_o(Led_o), .AnsDataReg_o(data), //Spi0 .Spi0CtrlReg_o(Spi0Ctrl), .Spi0ClkReg_o(Spi0Clk), .Spi0CsDelayReg_o(Spi0CsDelay), .Spi0CsCtrlReg_o(Spi0CsCtrl), .Spi0TxFifoCtrlReg_o(Spi0TxFifoCtrl), .Spi0RxFifoCtrlReg_o(Spi0RxFifoCtrl), .Spi0TxFifoReg_o(Spi0TxFifo), .Spi0RxFifoReg_o(Spi0RxFifo), //Spi1 .Spi1CtrlReg_o(Spi1Ctrl), .Spi1ClkReg_o(Spi1Clk), .Spi1CsDelayReg_o(Spi1CsDelay), .Spi1CsCtrlReg_o(Spi1CsCtrl), .Spi1TxFifoCtrlReg_o(Spi1TxFifoCtrl), .Spi1RxFifoCtrlReg_o(Spi1RxFifoCtrl), .Spi1TxFifoReg_o(Spi1TxFifo), .Spi1RxFifoReg_o(Spi1RxFifo), //Spi2 .Spi2CtrlReg_o(Spi2Ctrl), .Spi2ClkReg_o(Spi2Clk), .Spi2CsDelayReg_o(Spi2CsDelay), .Spi2CsCtrlReg_o(Spi2CsCtrl), .Spi2TxFifoCtrlReg_o(Spi2TxFifoCtrl), .Spi2RxFifoCtrlReg_o(Spi2RxFifoCtrl), .Spi2TxFifoReg_o(Spi2TxFifo), .Spi2RxFifoReg_o(Spi2RxFifo), //Spi3 .Spi3CtrlReg_o(Spi3Ctrl), .Spi3ClkReg_o(Spi3Clk), .Spi3CsDelayReg_o(Spi3CsDelay), .Spi3CsCtrlReg_o(Spi3CsCtrl), .Spi3TxFifoCtrlReg_o(Spi3TxFifoCtrl), .Spi3RxFifoCtrlReg_o(Spi3RxFifoCtrl), .Spi3TxFifoReg_o(Spi3TxFifo), .Spi3RxFifoReg_o(Spi3RxFifo), //Spi4 .Spi4CtrlReg_o(Spi4Ctrl), .Spi4ClkReg_o(Spi4Clk), .Spi4CsDelayReg_o(Spi4CsDelay), .Spi4CsCtrlReg_o(Spi4CsCtrl), .Spi4TxFifoCtrlReg_o(Spi4TxFifoCtrl), .Spi4RxFifoCtrlReg_o(Spi4RxFifoCtrl), .Spi4TxFifoReg_o(Spi4TxFifo), .Spi4RxFifoReg_o(Spi4RxFifo), //Spi5 .Spi5CtrlReg_o(Spi5Ctrl), .Spi5ClkReg_o(Spi5Clk), .Spi5CsDelayReg_o(Spi5CsDelay), .Spi5CsCtrlReg_o(Spi5CsCtrl), .Spi5TxFifoCtrlReg_o(Spi5TxFifoCtrl), .Spi5RxFifoCtrlReg_o(Spi5RxFifoCtrl), .Spi5TxFifoReg_o(Spi5TxFifo), .Spi5RxFifoReg_o(Spi5RxFifo), //Spi6 .Spi6CtrlReg_o(Spi6Ctrl), .Spi6ClkReg_o(Spi6Clk), .Spi6CsDelayReg_o(Spi6CsDelay), .Spi6CsCtrlReg_o(Spi6CsCtrl), .Spi6TxFifoCtrlReg_o(Spi6TxFifoCtrl), .Spi6RxFifoCtrlReg_o(Spi6RxFifoCtrl), .Spi6TxFifoReg_o(Spi6TxFifo), .Spi6RxFifoReg_o(Spi6RxFifo), .SpiTxRxEnReg_o(SpiTxRxEn), .GPIOAReg_o(GPIOA) ); genvar i; generate for (i = 0; i < SpiNum; i = i + 1) begin: SpiGen QuadSPIm QuadSPIm_inst ( .Clk_i(Clk100_i), .Start_i(ten[i]), .Rst_i(Rst_i|SpiRst_i[i]), .SPIdata(32'h2aaa00aa), .Sck_o(Sck[i]), .Ss_o(Ss[i]), .Mosi0_i(Mosi0[i]), .Mosi1_i(Mosi1[i]), .Mosi2_i(Mosi2[i]), .Mosi3_i(Mosi3[i]), .WidthSel_i(3), .PulsePol_i(0), .EndianSel_i(1), .LAG_i(0), .LEAD_i(0), .SELST_i(1) ); end endgenerate InitRst InitRst_inst ( .clk_i(gclk), .signal_o(Rst_i) ); endmodule