set_property PACKAGE_PIN C15 [get_ports {SmcAddr_i[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[0]}] set_property PACKAGE_PIN C13 [get_ports {SmcAddr_i[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[1]}] set_property PACKAGE_PIN D15 [get_ports {SmcAddr_i[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[2]}] set_property PACKAGE_PIN C14 [get_ports {SmcAddr_i[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[3]}] set_property PACKAGE_PIN E15 [get_ports {SmcAddr_i[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[4]}] set_property PACKAGE_PIN D13 [get_ports {SmcAddr_i[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[5]}] set_property PACKAGE_PIN F15 [get_ports {SmcAddr_i[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[6]}] set_property PACKAGE_PIN E14 [get_ports {SmcAddr_i[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[7]}] set_property PACKAGE_PIN J15 [get_ports {SmcAddr_i[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[8]}] set_property PACKAGE_PIN F14 [get_ports {SmcAddr_i[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[9]}] set_property PACKAGE_PIN K15 [get_ports {SmcAddr_i[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[10]}] set_property PACKAGE_PIN B15 [get_ports {SmcData_i[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[0]}] set_property PACKAGE_PIN B14 [get_ports {SmcData_i[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[1]}] set_property PACKAGE_PIN B11 [get_ports {SmcData_i[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[2]}] set_property PACKAGE_PIN B12 [get_ports {SmcData_i[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[3]}] set_property PACKAGE_PIN A12 [get_ports {SmcData_i[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[4]}] set_property PACKAGE_PIN B9 [get_ports {SmcData_i[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[5]}] set_property PACKAGE_PIN K14 [get_ports {SmcData_i[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[6]}] set_property PACKAGE_PIN A11 [get_ports {SmcData_i[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[7]}] set_property PACKAGE_PIN A6 [get_ports {SmcData_i[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[8]}] set_property PACKAGE_PIN A13 [get_ports {SmcData_i[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[9]}] set_property PACKAGE_PIN A10 [get_ports {SmcData_i[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[10]}] set_property PACKAGE_PIN B6 [get_ports {SmcData_i[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[11]}] set_property PACKAGE_PIN A5 [get_ports {SmcData_i[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[12]}] set_property PACKAGE_PIN B10 [get_ports {SmcData_i[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[13]}] set_property PACKAGE_PIN A8 [get_ports {SmcData_i[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[14]}] set_property PACKAGE_PIN A14 [get_ports {SmcData_i[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[15]}] set_property PACKAGE_PIN C6 [get_ports Led_o] set_property IOSTANDARD LVCMOS33 [get_ports Led_o] set_property PACKAGE_PIN A9 [get_ports SmcAwe_i] set_property IOSTANDARD LVCMOS33 [get_ports SmcAwe_i] set_property PACKAGE_PIN C5 [get_ports SmcAre_i] set_property IOSTANDARD LVCMOS33 [get_ports SmcAre_i] set_property PACKAGE_PIN C8 [get_ports SmcAoe_i] set_property IOSTANDARD LVCMOS33 [get_ports SmcAoe_i] set_property PACKAGE_PIN L15 [get_ports {SmcBe_i[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[1]}] set_property PACKAGE_PIN L14 [get_ports {SmcBe_i[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[0]}] #========================================================================== # SPI INTERFACES #SPI0 set_property PACKAGE_PIN K1 [get_ports {Sck_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[0]}] set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}] set_property PACKAGE_PIN K2 [get_ports {SsFlash_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[0]}] set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}] set_property PACKAGE_PIN J3 [get_ports {Mosi1_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[0]}] set_property PACKAGE_PIN H2 [get_ports {Mosi2_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}] set_property PACKAGE_PIN L1 [get_ports {Mosi3_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}] set_property PACKAGE_PIN J2 [get_ports {SpiRst_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[0]}] set_property PACKAGE_PIN M13 [get_ports {Ld_i[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[0]}] #SPI1 set_property PACKAGE_PIN N2 [get_ports {Sck_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[1]}] set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}] set_property PACKAGE_PIN P1 [get_ports {SsFlash_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[1]}] set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}] set_property PACKAGE_PIN R2 [get_ports {Mosi1_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[1]}] set_property PACKAGE_PIN N1 [get_ports {Mosi2_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[1]}] set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[1]}] set_property PACKAGE_PIN P2 [get_ports {SpiRst_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[1]}] set_property PACKAGE_PIN N11 [get_ports {Ld_i[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[1]}] #SPI2 set_property PACKAGE_PIN E2 [get_ports {Sck_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[2]}] set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}] set_property PACKAGE_PIN F1 [get_ports {SsFlash_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[2]}] set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}] set_property PACKAGE_PIN D2 [get_ports {Mosi1_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[2]}] set_property PACKAGE_PIN F2 [get_ports {Mosi2_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[2]}] set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[2]}] set_property PACKAGE_PIN E3 [get_ports {SpiRst_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[2]}] set_property PACKAGE_PIN N9 [get_ports {Ld_i[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[2]}] #SPI3 set_property PACKAGE_PIN R10 [get_ports {Sck_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[3]}] set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}] set_property PACKAGE_PIN N10 [get_ports {SsFlash_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[3]}] set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}] set_property PACKAGE_PIN R8 [get_ports {Mosi1_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[3]}] set_property PACKAGE_PIN R11 [get_ports {Mosi2_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[3]}] set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[3]}] set_property PACKAGE_PIN R9 [get_ports {SpiRst_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[3]}] set_property PACKAGE_PIN N13 [get_ports {Ld_i[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[3]}] #SPI4 set_property PACKAGE_PIN R14 [get_ports {Sck_o[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[4]}] set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}] set_property PACKAGE_PIN P14 [get_ports {SsFlash_o[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[4]}] set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}] set_property PACKAGE_PIN P12 [get_ports {Mosi1_o[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[4]}] set_property PACKAGE_PIN M15 [get_ports {Mosi2_o[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[4]}] set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[4]}] set_property PACKAGE_PIN N15 [get_ports {SpiRst_o[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[4]}] set_property PACKAGE_PIN P15 [get_ports {Ld_i[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[4]}] #SPI5 set_property PACKAGE_PIN P6 [get_ports {Sck_o[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[5]}] set_property PACKAGE_PIN R5 [get_ports {Ss_o[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}] set_property PACKAGE_PIN R6 [get_ports {SsFlash_o[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[5]}] set_property PACKAGE_PIN R4 [get_ports {Mosi0_o[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}] set_property PACKAGE_PIN R3 [get_ports {Mosi1_o[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[5]}] set_property PACKAGE_PIN N7 [get_ports {Mosi2_o[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[5]}] set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}] set_property PACKAGE_PIN N6 [get_ports {SpiRst_o[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[5]}] set_property PACKAGE_PIN N12 [get_ports {Ld_i[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[5]}] #SPI6 set_property PACKAGE_PIN B5 [get_ports {Sck_o[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[6]}] set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}] set_property PACKAGE_PIN A4 [get_ports {SsFlash_o[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[6]}] set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}] set_property PACKAGE_PIN C4 [get_ports {Mosi1_o[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[6]}] set_property PACKAGE_PIN B4 [get_ports {Mosi2_o[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[6]}] set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[6]}] set_property PACKAGE_PIN A2 [get_ports {SpiRst_o[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[6]}] set_property PACKAGE_PIN M8 [get_ports {Ld_i[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[6]}] set_property PACKAGE_PIN M7 [get_ports LD_o] set_property IOSTANDARD LVCMOS33 [get_ports LD_o] #========================================================================== # INPUT CLOCKS set_property PACKAGE_PIN M10 [get_ports Clk123_i] set_property IOSTANDARD LVCMOS33 [get_ports Clk123_i] create_clock -period 8.130 -name Clk123_i -waveform {0.000 4.065} -add [get_ports Clk123_i] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF] # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets writeEn_i_IBUF] # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets readEn_i_IBUF] create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list gclk]] set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0] set_property port_width 7 [get_debug_ports u_ila_0/probe0] connect_debug_port u_ila_0/probe0 [get_nets [list {Ss_o_OBUF[0]} {Ss_o_OBUF[1]} {Ss_o_OBUF[2]} {Ss_o_OBUF[3]} {Ss_o_OBUF[4]} {Ss_o_OBUF[5]} {Ss_o_OBUF[6]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1] set_property port_width 16 [get_debug_ports u_ila_0/probe1] connect_debug_port u_ila_0/probe1 [get_nets [list {SmcData_i_IBUF[0]} {SmcData_i_IBUF[1]} {SmcData_i_IBUF[2]} {SmcData_i_IBUF[3]} {SmcData_i_IBUF[4]} {SmcData_i_IBUF[5]} {SmcData_i_IBUF[6]} {SmcData_i_IBUF[7]} {SmcData_i_IBUF[8]} {SmcData_i_IBUF[9]} {SmcData_i_IBUF[10]} {SmcData_i_IBUF[11]} {SmcData_i_IBUF[12]} {SmcData_i_IBUF[13]} {SmcData_i_IBUF[14]} {SmcData_i_IBUF[15]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2] set_property port_width 11 [get_debug_ports u_ila_0/probe2] connect_debug_port u_ila_0/probe2 [get_nets [list {SmcAddr_i_IBUF[0]} {SmcAddr_i_IBUF[1]} {SmcAddr_i_IBUF[2]} {SmcAddr_i_IBUF[3]} {SmcAddr_i_IBUF[4]} {SmcAddr_i_IBUF[5]} {SmcAddr_i_IBUF[6]} {SmcAddr_i_IBUF[7]} {SmcAddr_i_IBUF[8]} {SmcAddr_i_IBUF[9]} {SmcAddr_i_IBUF[10]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 1 [get_debug_ports u_ila_0/probe3] connect_debug_port u_ila_0/probe3 [get_nets [list SmcAre_i_IBUF]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 1 [get_debug_ports u_ila_0/probe4] connect_debug_port u_ila_0/probe4 [get_nets [list SmcAwe_i_IBUF]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] connect_debug_port dbg_hub/clk [get_nets gclk]