module SmcDataMux 
#(
    parameter	CmdRegWidth	=	32,
    parameter	AddrRegWidth=	12,
	
	parameter	FifoNum	=	7,
	
	parameter	Fifo0WriteAddr	=	12'h0+12'h16,
	parameter	Fifo1WriteAddr	=	12'h50+12'h16,
	parameter	Fifo2WriteAddr	=	12'hF0+12'h16,
	parameter	Fifo3WriteAddr	=	12'h140+12'h16,
	parameter	Fifo4WriteAddr	=	12'h190+12'h16,
	parameter	Fifo5WriteAddr	=	12'h1e0+12'h16,
	parameter	Fifo6WriteAddr	=	12'h230+12'h16
)
(
    input	Clk_i,
    input	Rst_i,

	input	SmcVal_i,
	input	[CmdRegWidth-1:0]	SmcData_i,
    input	[AddrRegWidth-1:0]	SmcAddr_i,

	output	reg	ToRegMapVal_o,
	output	reg	[CmdRegWidth-1:0]	ToRegMapData_o,
    output	reg	[AddrRegWidth-1:0]	ToRegMapAddr_o,
	
	output	reg	[FifoNum-1:0]	ToFifoVal_o,
	output	reg	[CmdRegWidth*FifoNum-1:0]	ToFifoData_o
	
);
//================================================================================
//	REG/WIRE
//================================================================================

//================================================================================
//	ASSIGNMENTS
//================================================================================

//================================================================================
//	LOCALPARAMS
//================================================================================

//================================================================================
//	CODING
//================================================================================

always	@(posedge	Clk_i	or	posedge	Rst_i)	begin
	if	(Rst_i)	begin
		ToRegMapVal_o	<=	1'b0;
		ToRegMapData_o	<=	32'h0;
		ToRegMapAddr_o	<=	12'h0;
		
		ToFifoVal_o		<=	7'h0;
		ToFifoData_o	<=	32'h0;
	end	else	begin
		if	(SmcAddr_i	==	Fifo0WriteAddr||SmcAddr_i==Fifo1WriteAddr||SmcAddr_i==Fifo2WriteAddr||SmcAddr_i==Fifo3WriteAddr||SmcAddr_i==Fifo4WriteAddr||SmcAddr_i==Fifo5WriteAddr||SmcAddr_i==Fifo6WriteAddr)	begin	
			case(SmcAddr_i)	
				Fifo0WriteAddr:	begin
									ToFifoVal_o[0]	<=	SmcVal_i;
									ToFifoData_o[32*0+:32]	<=	SmcData_i;
								end
				Fifo1WriteAddr:	begin
									ToFifoVal_o[1]	<=	SmcVal_i;
									ToFifoData_o[32*1-1+:32]	<=	SmcData_i;
								end
				Fifo2WriteAddr:	begin
									ToFifoVal_o[2]	<=	SmcVal_i;
									ToFifoData_o[32*2-1+:32]	<=	SmcData_i;
								end
				Fifo3WriteAddr:	begin
									ToFifoVal_o[3]	<=	SmcVal_i;
									ToFifoData_o[32*3-1+:32]	<=	SmcData_i;
								end
				Fifo4WriteAddr:	begin
									ToFifoVal_o[4]	<=	SmcVal_i;
									ToFifoData_o[32*4-1+:32]	<=	SmcData_i;
								end
				Fifo5WriteAddr:	begin
									ToFifoVal_o[5]	<=	SmcVal_i;
									ToFifoData_o[32*5-1+:32]	<=	SmcData_i;
								end
				Fifo6WriteAddr:	begin
									ToFifoVal_o[6]	<=	SmcVal_i;
									ToFifoData_o[32*6-1+:32]	<=	SmcData_i;
								end
			endcase
		end	else	begin
			ToRegMapVal_o	<=	SmcVal_i;
			ToRegMapData_o	<=	SmcData_i;
			ToRegMapAddr_o	<=	SmcAddr_i;
		end
	end
end
endmodule