`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 10.10.2018 01:07:38
// Design Name: 
// Module Name: sram_ctrl2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module	MasterFpgaTop
(
	input	Clk_i,                       
	input	RstN_i,                     
	input	ForceRstN_i,                     

	input	[15:0]	SmcD_i,
	input	[24:0]	SmcA_i,
	input	SmcAwe_i,
	input	SmcAmsN_i,
	input	SmcAoe_i,	
	input	SmcAre_i,	
	input	[1:0]	SmcBe_i,
	
	output	[15:0]	Data_o,
	output	[24:0]	Addr_o,
	output	Val_o
);

//================================================================================
//  REG/WIRE
	
	wire	[24:0]	sramSmcAddr;
	wire	[31:0]	sramSmcData;
	wire	sramVal;

//================================================================================
//  LOCALPARAM
	
//================================================================================
//  ASSIGNMENTS	

//================================================================================
//  CODING
	

SramRx	SramRx
(
	.Clk_i		(Clk_i	),
	.RstN_i		(RstN_i),
	.ForceRstN_i(ForceRstN_i),

	.SmcD_i		(SmcD_i),
	.SmcA_i		(SmcA_i),
	.SmcAwe_i	(SmcAwe_i),
	.SmcAmsN_i	(SmcAmsN_i),
	.SmcAoe_i	(SmcAoe_i),
	.SmcAre_i	(SmcAre_i),
	.SmcBe_i	(SmcBe_i),
	
	.Data_o		(sramSmcData),
	.Addr_o		(sramSmcAddr),
	.Val_o		(sramVal)
);

endmodule