`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 10.10.2018 01:07:38
// Design Name: 
// Module Name: sram_ctrl2
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module	S5443_3TopTb
(
	input	Clk_i
);

//================================================================================
//  REG/WIRE
	reg	clk123Dsp;
	wire	start;
	reg	rstN;
	reg	ForceRstN;
	
	wire	[15:0]	data;
	wire	[10:0]	addr;
	wire	awe;
	wire	amsn;
	wire	aoe;
	wire	are;
	wire	[1:0]	be;
	
	reg	[31:0]	tbCnt;
//================================================================================
//  LOCALPARAM
	
//================================================================================
//  ASSIGNMENTS	
	always	#8.13	clk123Dsp	=	~clk123Dsp;
	assign	start	=	(tbCnt==50||tbCnt==51);
//================================================================================
//  CODING

initial	begin
	rstN		=	0;
	ForceRstN	=	0;
	clk123Dsp	=	1;
	#20
	rstN		=	1;
	ForceRstN	=	1;
	
end

always	@(posedge	clk123Dsp)	begin
	if	(rstN)	begin
		tbCnt	<=	tbCnt+32'd1;
	end	else	begin
		tbCnt	<=	0;
	end
end

DspSmcModel	DspSmcModel
(
	.Clk120MHz_i	(clk123Dsp),
	.RstN_i			(rstN),
	.SmcD_o			(data),
	.SmcA_o			(addr),
	.SmcAwe_o		(awe),
	.SmcAmsN_o		(amsn),
	.SmcAoe_o		(aoe),
	.SmcAre_o		(are),
	.SmcBe_o		(be),
	
	.Start_i		(start)
);

S5443_3Top S5443_3Top
(
	.Clk123_i	(clk123Dsp),
	.SmcAddr_i	(addr),
	.SmcData_i	(data),
    
	.SmcAwe_i	(awe),
	.SmcAmsN_i	(amsn),
	
	.SmcAre_i	(are),
	.SmcBe_i	(be),
	.SmcAoe_i	(aoe),
	.LD_i		(),
	
	.Led_o		(),
	
	.Mosi0_o	(),
	.Mosi1_o	(),
	.Mosi2_o	(),
	.Mosi3_o	(),
	.Ss_o		(),
	.SsFlash_o	(),
	.Sck_o		(),
	.SpiRst_o	(),
	.LD_o		()
);
endmodule