xilinx.com xci unknown 1.0 clk_wiz_0 false 100000000 false 100000000 false 100000000 false 100000000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 100000000 0 0 0.000 1 LEVEL_HIGH 100000000 0 0 0.000 0 0 100000000 0 0 0.000 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.000 AXI4LITE READ_WRITE 0 0 0 0 0 0 MMCM cddcdone cddcreq 0000 0000 clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 81.30000000000001 162.49 0000 0000 99.93750 0000 0000 79.95000 BUFG 50.0 false 99.93750 0.000 50.000 100 0.000 1 0000 0000 61.50000 BUFG 50.0 false 79.95000 0.000 50.000 80.000 0.000 1 1 0000 0000 100.000 BUFG 50.0 false 61.50000 0.000 50.000 61.000 0.000 1 1 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 VCO clk_in_sel clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 CLK_VALID NA daddr dclk den din 0000 1 1.25 1.639344262295082 1.0 1.0 1.0 1.0 dout drdy dwe 49.000 1.000 0 0 0 0 0 0 0 0 FDBK_AUTO 0000 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_________123.000____________0.010 no_secondary_input_clock input_clk_stopped 0 Units_MHz No_Jitter locked 0000 0000 0000 false false false false false false false false OPTIMIZED 13.000 0.000 FALSE 8.130 10.000 16.000 0.500 0.000 FALSE 20 0.500 0.000 FALSE 26 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE INTERNAL 1 None 0.010 0.010 FALSE 64.000 2.000 3 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) clk_out1__99.93750______0.000______50.0_______90.934_____71.092 clk_out2__79.95000______0.000______50.0_______94.713_____71.092 clk_out3__61.50000______0.000______50.0_______99.369_____71.092 no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 1 0 128.000 1.000 WAVEFORM UNKNOWN false false false false false OPTIMIZED 1 0.000 1.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 No notes 0.010 power_down 0000 1 clk_in1 PLL AUTO 123.000 0.010 10.000 Single_ended_clock_capable_pin psclk psdone psen psincdec 100.0 0 reset 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 4000 0.004 STATUS 11 32 100.0 100.0 100.0 100.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1866.000 800.000 clk_wiz_0 MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 81.30000000000001 0.010 162.49 0.010 BUFG 90.934 false 71.092 50.000 100 0.000 1 true BUFG 94.713 false 71.092 50.000 80.000 0.000 1 true BUFG 99.369 false 71.092 50.000 61.000 0.000 1 true BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom clk_in_sel clk_out1 false clk_out2 false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto clk_wiz_0 daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 13 0.000 false 8.130 10.000 16 0.500 0.000 false 20 0.500 0.000 false 26 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false INTERNAL 1 None 0.010 0.010 false 3 true false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 8.130 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 clk_in1 PLL mmcm_adv 123.000 0.010 10.000 Single_ended_clock_capable_pin psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false true false false false true false true false false false spartan7 xc7s25 csga225 VERILOG MIXED -2 TRUE TRUE IP_Flow 6 TRUE ../../../../S5443_3.gen/sources_1/ip/clk_wiz_0 . 2020.2 OUT_OF_CONTEXT