S5443_V3/AdcInit/ResetFilter.v

module ResetFilter (
    clk_i,
    rst_i,
    perm_i,
    filtered_rst_o
);

    parameter   STAGE_NUM   = 1;
    parameter   RESET_FRONT = "RISING"; //  FALLING

    input   clk_i;
    input   rst_i;
    input   perm_i;
    output  filtered_rst_o;

    reg [STAGE_NUM-1:0] rst_filter;

    assign  filtered_rst_o  = rst_filter[STAGE_NUM-1];

generate
    if (RESET_FRONT == "RISING") begin
        if (STAGE_NUM < 2) begin
            always @(posedge clk_i or posedge rst_i) begin
                if (rst_i) begin
                    rst_filter  <= 1'b1;
                end else begin
                    rst_filter  <= perm_i;
                end
            end
        end else begin
            always @(posedge clk_i or posedge rst_i) begin
                if (rst_i) begin
                    rst_filter  <= {STAGE_NUM{1'b1}};
                end else begin
                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
                end
            end        
        end
    end else begin
        if (STAGE_NUM < 2) begin
            always @(posedge clk_i or negedge rst_i) begin
                if (!rst_i) begin
                    rst_filter  <= 1'b1;
                end else begin
                    rst_filter  <= perm_i;
                end
            end
        end else begin
            always @(posedge clk_i or negedge rst_i) begin
                if (!rst_i) begin
                    rst_filter  <= {STAGE_NUM{1'b1}};
                end else begin
                    rst_filter  <= {rst_filter[STAGE_NUM-2:0], perm_i};
                end
            end        
        end    
    end
endgenerate

endmodule