S5443_V3/SRAM/QuadSPIs.v

module QuadSPIs (
    input Clk_i,
    input Rst_i,

    input Sck_i,
    input Ss_i,
    input Mosi0_i,
    input Mosi1_i,
    input Mosi2_i,
    input Mosi3_i,

    output reg [23:0] Data_o,
    output reg [7:0] Addr_o,
    output reg Val_o
);

//================================================================================
//	REG/WIRE
//================================================================================

reg ssReg;
reg ssRegR;
reg RorWFlag;

reg [3:0] cnt; 
reg [7:0] addrReg;
reg [7:0] shiftReg0R;
reg [7:0] shiftReg1R;
reg [7:0] shiftReg2R;
reg [7:0] shiftReg0RR;
reg [7:0] shiftReg1RR;
reg [7:0] shiftReg2RR;
reg [7:0] shiftReg0;
reg [7:0] shiftReg1;
reg [7:0] shiftReg2;
//================================================================================
//	CODING
//================================================================================

always @(posedge Clk_i) begin 
    if (Rst_i) begin 
        Data_o <= 24'h0;
    end
    else begin 
        if (ssReg && !ssRegR) begin 
            Data_o <= {shiftReg2, shiftReg1, shiftReg0};
        end
        else begin 
            Data_o <= 24'h0;
        end
    end
end

always @(posedge Clk_i) begin 
    if (Rst_i) begin 
        Addr_o <= 8'h0;
    end
    else begin 
        if (ssReg && !ssRegR) begin 
            Addr_o <= addrReg;
        end
    end
end


always @(posedge Sck_i) begin 
    if (Rst_i) begin 
        shiftReg0 <= 8'h0;
    end
    else begin 
        if (!Ss_i) begin 
            shiftReg0 <= {shiftReg0[6:0], Mosi0_i};
        end
        else begin 
            shiftReg0 <= 8'h0;
        end
    end
end


always @(posedge Sck_i ) begin 
    if (Rst_i) begin 
        shiftReg1 <= 8'h0;
    end
    else begin 
        if (!Ss_i) begin 
            shiftReg1 <= {shiftReg1[6:0], Mosi1_i};
        end
        else begin 
            shiftReg1 <= 8'h0;
        end
    end
end


always @(posedge Sck_i ) begin 
    if (Rst_i) begin 
        shiftReg2 <= 8'h0;
    end
    else begin 
        if (!Ss_i) begin 
            shiftReg2 <= {shiftReg2[6:0], Mosi2_i};
        end
        else begin 
            shiftReg2 <= 8'h0;
        end
    end
end


always @(posedge Sck_i ) begin 
    if (Rst_i) begin 
        addrReg <= 8'h0;
    end
    else begin 
        if (!Ss_i) begin 
            addrReg <= {addrReg[6:0], Mosi3_i};
        end
        else begin 
            addrReg <= 8'h0;
        end
    end
end


always	@(posedge	Clk_i)	begin
	ssReg	<=	Ss_i;
	ssRegR	<=	ssReg;
    shiftReg0R <= shiftReg0;
    shiftReg1R <= shiftReg1;
    shiftReg2R <= shiftReg2;
    shiftReg0RR <= shiftReg0R;
    shiftReg1RR <= shiftReg1R;
    shiftReg2RR <= shiftReg2R;
end


always @(posedge Clk_i) begin 
    if (ssReg && !ssRegR) begin 
        Val_o <= 1'b1;
    end
    else begin 
        Val_o <= 1'b0;
    end
end




endmodule