S5443_V3/sources_1/new/S5443_3Top.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 10/30/2023 11:24:31 AM
// Design Name: 
// Module Name: S5443_3Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module S5443_3Top #(
    parameter CmdRegWidth = 32,
    parameter AddrRegWidth = 12,
    parameter SpiNum = 7

)(
    input Clk123_i,
    input [AddrRegWidth-2:0] Addr_i,
    inout [CmdRegWidth/2-1:0] Data_i,
    input [SpiNum-1:0] SpiRst_i,
    input writeEn_i,
    input readEn_i,
    // input DspRst_i,
    input [1:0] BE_i,
    input outputEn_i,

    output  Led_o,
   
    output  [SpiNum-1:0] Mosi0_o,
    output  [SpiNum-1:0] Mosi1_o,
    output  [SpiNum-1:0] Mosi2_o,
    output  [SpiNum-1:0] Mosi3_o,
    output  [SpiNum-1:0] Ss_o,
    output  [SpiNum-1:0] Sck_o

);

//================================================================================
//  REG/WIRE
//================================================================================
wire Clk100_i;
wire [SpiNum-1:0]Sck;
wire [SpiNum-1:0] Ss; 
wire [SpiNum-1:0]Mosi0;
wire [SpiNum-1:0]Mosi1;
wire [SpiNum-1:0]Mosi2;
wire [SpiNum-1:0]Mosi3;
wire [SpiNum-1:0] ten;
wire clk80;
wire clk61;
wire Rst_i;
wire gclk;
wire [15:0] baudRate;
wire [19:0] baudRateexp;

//================================================================================
//  ASSIGNMENTS
//================================================================================
assign addr = {Addr_i, 1'b0};
assign Data_i = (!outputEn_i) ? data : 16'bz;
assign ten = 8'b00000001;
assign Mosi0_o = Mosi0;
assign Mosi1_o = Mosi1;
assign Mosi2_o = Mosi2;
assign Mosi3_o = Mosi3;
assign Ss_o = Ss;
assign Sck_o = Sck;
assign baudRate = 16'h4;
assign baudRateexp = baudRate*13+1;
//================================================================================
//  CODING
//================================================================================	

BUFG BUFG_inst (
   .O(gclk), // 1-bit output: Clock output
   .I(Clk123_i)  // 1-bit input: Clock input
);


  clk_wiz_0 ClkGen
   (
   .s_axi_aclk      (),        // input s_axi_aclk                        
   .s_axi_aresetn   (),     // input s_axi_aresetn,                                                          
   .s_axi_awaddr    (),      // input [10 : 0] s_axi_awaddr,                              
   .s_axi_awvalid   (),     // input s_axi_awvalid,                                                          
   .s_axi_awready   (),     // output s_axi_awready,                                                         
   .s_axi_wdata     (),       // input [31 : 0] s_axi_wdata,                             
   .s_axi_wstrb     (),       // input [3 : 0] s_axi_wstrb,                         
   .s_axi_wvalid    (),      // input s_axi_wvalid,                                                         
   .s_axi_wready    (),      // output s_axi_wready,                                                        
   .s_axi_bresp     (),       // output [1 : 0] s_axi_bresp,                                               
   .s_axi_bvalid    (),      // output s_axi_bvalid,                                                        
   .s_axi_bready    (),      // input s_axi_bready,                                                         
   .s_axi_araddr    (),      // input [10 : 0] s_axi_araddr,                              
   .s_axi_arvalid   (),     // input s_axi_arvalid,                                                          
   .s_axi_arready   (),     // output s_axi_arready,                                                         
   .s_axi_rdata     (),       // output [31 : 0] s_axi_rdata,                            
   .s_axi_rresp     (),       // output [1 : 0] s_axi_rresp,                                               
   .s_axi_rvalid    (),      // output s_axi_rvalid,                                                        
   .s_axi_rready    (),      // input s_axi_rready,                                                         
    // Clock out ports
    .clk_out1(Clk100_i),     // output clk_out1
    // Status and control signals
    .locked(),       // output locked
   // Clock in ports
    .clk_in1(gclk));      // input clk_in1


RegMap #(
    .CmdRegWidth(32),
    .AddrRegWidth(12)
)
RegMap_inst (
    .Clk_i(gclk),
    .Rst_i(Rst_i),
    .Data_i(Data_i),
    .Addr_i(addr),
    .wrEn_i(writeEn_i),
    .rdEn_i(readEn_i),
    .BE_i(BE_i),
    .Led_o(Led_o),
    .AnsDataReg_o(data)

);




genvar i;

generate
    for  (i = 0; i < SpiNum; i = i + 1) begin: SpiGen
        QuadSPIm QuadSPIm_inst (
            .Clk_i(Clk100_i),
            .Start_i(ten[i]),
            .Rst_i(Rst_i|SpiRst_i[i]),
            .SPIdata(32'h2aaa00aa),
            .Sck_o(Sck[i]),
            .Ss_o(Ss[i]),
            .Mosi0_i(Mosi0[i]),
            .Mosi1_i(Mosi1[i]),
            .Mosi2_i(Mosi2[i]),
            .Mosi3_i(Mosi3[i]),
            .WidthSel_i(3),
            .PulsePol_i(0),
            .EndianSel_i(1),
            .LAG_i(0),
            .LEAD_i(0),
            .SELST_i(1)
        );
    end
endgenerate


InitRst InitRst_inst (
    .clk_i(gclk),
    .signal_o(Rst_i)

);


endmodule