S5443_V3/sources_1/new/MMCM/MmcmWrapper.v

module MmcmWrapper 
#(
	parameter	SpiNum	=	7
)
(
   input	Clk_i,
   input	Rst_i,
   input [6:0] ClkDiv1_i,
   input [15:0] ClkDiv2_i,
   input [15:0] ClkDiv3_i,
   input [15:0] ClkDiv4_i,
   input [15:0] ClkDiv5_i,
   input [15:0] ClkDiv6_i,
   input [15:0] ClkDiv7_i,



	output	[SpiNum-1:0]	SpiClk_o
);
//================================================================================
//	REG/WIRE
//================================================================================
	
wire            clk0out;
wire            clk1out;
wire            clk2out;
wire            clk3out;
wire            clk4out;
wire            clk5out;
wire            clk6out;
wire            SRDY;
wire            locked;

reg [1:0] SM = STARTUP;
reg SSTEP;

reg sStep1;
reg sStep2;
reg sStep3;
reg sStep4;
reg sStep5;
reg sStep6;
reg sStep7;


reg clkDiv1R;
reg clkDiv2R;
reg clkDiv3R;
reg clkDiv4R;
reg clkDiv5R;
reg clkDiv6R;
reg clkDiv7R;



//================================================================================
//	ASSIGNMENTS
//================================================================================
	assign SpiClk_o[0]	=	clk0out;
   assign SpiClk_o[1]	=	clk1out;
   assign SpiClk_o[2]	=	clk2out;
   assign SpiClk_o[3]	=	clk3out;
   assign SpiClk_o[4]	=	clk4out;
   assign SpiClk_o[5]	=	clk5out;
   assign SpiClk_o[6]	=	clk6out;

//================================================================================
//	LOCALPARAMS
//================================================================================
parameter [1:0] STARTUP = 0, STATE0 = 1, STATE1 = 2, UNDEFINED = 3;

//================================================================================
//	CODING
//================================================================================
top_mmcme2 MMCE2_inst (
   .SSTEP      (),
   .STATE      (),
   .RST        (Rst_i),
   .CLKIN      (Clk_i),
   .SRDY       (SRDY),
   .LOCKED_OUT (locked),
   .CLK0OUT    (clk0out),
   .CLK1OUT    (clk1out),
   .CLK2OUT    (clk2out),
   .CLK3OUT    (clk3out),
   .CLK4OUT    (clk4out),
   .CLK5OUT    (clk5out),
   .CLK6OUT    (clk6out)









);

always @(posedge Clk_i) begin 
   if (Rst_i) begin 
      clkDiv1R <= 1'b0;
      clkDiv2R <= 1'b0;
      clkDiv3R <= 1'b0;
      clkDiv4R <= 1'b0;
      clkDiv5R <= 1'b0;
      clkDiv6R <= 1'b0;
      clkDiv7R <= 1'b0;
   end
   else begin 
      clkDiv1R <= ClkDiv1_i;
      clkDiv2R <= ClkDiv2_i;
      clkDiv3R <= ClkDiv3_i;
      clkDiv4R <= ClkDiv4_i;
      clkDiv5R <= ClkDiv5_i;
      clkDiv6R <= ClkDiv6_i;
      clkDiv7R <= ClkDiv7_i;
   end
end


always @(*) begin 
   if (Rst_i) begin 
      sStep1<= 1'b0;
   end
   else begin 
      if (clkDiv1R != ClkDiv1_i) begin 
         sStep1 <= 1'b1;
      end
      else begin 
         sStep1 <= 1'b0;
      end
   end
end

always @(*) begin 
   if (Rst_i) begin 
      sStep2<= 1'b0;
   end
   else begin 
      if (clkDiv2R != ClkDiv2_i) begin 
         sStep2 <= 1'b1;
      end
      else begin 
         sStep2 <= 1'b0;
      end
   end
end

always @(*) begin 
   if (Rst_i) begin 
      sStep3<= 1'b0;
   end
   else begin 
      if (clkDiv3R != ClkDiv3_i) begin 
         sStep3 <= 1'b1;
      end
      else begin 
         sStep3 <= 1'b0;
      end
   end
end

always @(*) begin 
   if (Rst_i) begin 
      sStep4<= 1'b0;
   end
   else begin 
      if (clkDiv4R!= ClkDiv4_i) begin 
         sStep4 <= 1'b1;
      end
      else begin 
         sStep4 <= 1'b0;
      end
   end
end

always @(*) begin 
   if (Rst_i) begin 
      sStep5<= 1'b0;
   end
   else begin 
      if (clkDiv5R != ClkDiv5_i) begin 
         sStep5 <= 1'b1;
      end
      else begin 
         sStep5 <= 1'b0;
      end
   end
end

always @(*) begin 
   if (Rst_i) begin 
      sStep6<= 1'b0;
   end
   else begin 
      if (clkDiv6R != ClkDiv6_i) begin 
         sStep6 <= 1'b1;
      end
      else begin 
         sStep6 <= 1'b0;
      end
   end
end

always @(*) begin 
   if (Rst_i) begin 
      sStep7<= 1'b0;
   end
   else begin 
      if (clkDiv7R != ClkDiv7_i) begin 
         sStep7 <= 1'b1;
      end
      else begin 
         sStep7 <= 1'b0;
      end
   end
end

// always @ (posedge Clk_i) begin 
//    if (Rst_i) begin
//       SM <= STARTUP;
//    end
//    else begin 
//       case (SM)
//          STARTUP: begin
//             SM <= STATE0;
//             SSTEP <= 1'b0;
//             STATE <= 1'b0;
//          end
//          STATE0: begin
//                if(locked) begin 
//                   if (ssTep1 | ssTep2 | ssTep3 | ssTep4 | ssTep5 | ssTep6 | ssTep7) begin 
//                      SSTEP <= 1'b1;
//                   end
//                   else begin 
//                      SSTEP <= 1'b0;
//                   end
//                end
//             end
//          end
//          STATE1: begin
//             if (SRDY) begin
//                SM <= STATE0;
//             end
//          end
//          UNDEFINED: begin
//             SM <= STARTUP;
//          end
//       endcase
//    end
// end



endmodule