S5443_V3/constrs_1/new/S5443_3.xdc

set_property PACKAGE_PIN C15 [get_ports {SmcAddr_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[0]}]
set_property PACKAGE_PIN C13 [get_ports {SmcAddr_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[1]}]
set_property PACKAGE_PIN D15 [get_ports {SmcAddr_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[2]}]
set_property PACKAGE_PIN C14 [get_ports {SmcAddr_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[3]}]
set_property PACKAGE_PIN E15 [get_ports {SmcAddr_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[4]}]
set_property PACKAGE_PIN D13 [get_ports {SmcAddr_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[5]}]
set_property PACKAGE_PIN F15 [get_ports {SmcAddr_i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[6]}]
set_property PACKAGE_PIN E14 [get_ports {SmcAddr_i[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[7]}]
set_property PACKAGE_PIN J15 [get_ports {SmcAddr_i[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[8]}]
set_property PACKAGE_PIN F14 [get_ports {SmcAddr_i[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[9]}]
set_property PACKAGE_PIN K15 [get_ports {SmcAddr_i[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcAddr_i[10]}]



set_property PACKAGE_PIN B15 [get_ports {SmcData_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[0]}]
set_property PACKAGE_PIN B14 [get_ports {SmcData_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[1]}]
set_property PACKAGE_PIN B11 [get_ports {SmcData_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[2]}]
set_property PACKAGE_PIN B12 [get_ports {SmcData_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[3]}]
set_property PACKAGE_PIN A12 [get_ports {SmcData_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[4]}]
set_property PACKAGE_PIN B9 [get_ports {SmcData_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[5]}]
set_property PACKAGE_PIN K14 [get_ports {SmcData_i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[6]}]
set_property PACKAGE_PIN A11 [get_ports {SmcData_i[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[7]}]
set_property PACKAGE_PIN A6 [get_ports {SmcData_i[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[8]}]
set_property PACKAGE_PIN A13 [get_ports {SmcData_i[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[9]}]
set_property PACKAGE_PIN A10 [get_ports {SmcData_i[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[10]}]
set_property PACKAGE_PIN B6 [get_ports {SmcData_i[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[11]}]
set_property PACKAGE_PIN A5 [get_ports {SmcData_i[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[12]}]
set_property PACKAGE_PIN B10 [get_ports {SmcData_i[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[13]}]
set_property PACKAGE_PIN A8 [get_ports {SmcData_i[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[14]}]
set_property PACKAGE_PIN A14 [get_ports {SmcData_i[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcData_i[15]}]

set_property PACKAGE_PIN B13 [get_ports SmcAmsN_i]
set_property IOSTANDARD LVCMOS33 [get_ports SmcAmsN_i]


set_property PACKAGE_PIN C6 [get_ports Led_o]
set_property IOSTANDARD LVCMOS33 [get_ports Led_o]

set_property PACKAGE_PIN A9 [get_ports SmcAwe_i]
set_property IOSTANDARD LVCMOS33 [get_ports SmcAwe_i]

set_property PACKAGE_PIN C5 [get_ports SmcAre_i]
set_property IOSTANDARD LVCMOS33 [get_ports SmcAre_i]

set_property PACKAGE_PIN C8 [get_ports SmcAoe_i]
set_property IOSTANDARD LVCMOS33 [get_ports SmcAoe_i]

set_property PACKAGE_PIN L15 [get_ports {SmcBe_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[1]}]
set_property PACKAGE_PIN L14 [get_ports {SmcBe_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SmcBe_i[0]}]


#==========================================================================
#	SPI INTERFACES

#SPI0
set_property PACKAGE_PIN K1 [get_ports {Sck_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[0]}]
set_property PACKAGE_PIN H1 [get_ports {Ss_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[0]}]
set_property PACKAGE_PIN K2 [get_ports {SsFlash_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[0]}]
set_property PACKAGE_PIN J1 [get_ports {Mosi0_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[0]}]
set_property PACKAGE_PIN J3 [get_ports {Mosi1_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[0]}]
set_property PACKAGE_PIN H2 [get_ports {Mosi2_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[0]}]
set_property PACKAGE_PIN L1 [get_ports {Mosi3_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[0]}]
set_property PACKAGE_PIN J2 [get_ports {SpiRst_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[0]}]
set_property PACKAGE_PIN M13 [get_ports {Ld_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[0]}]



#SPI1
set_property PACKAGE_PIN N2 [get_ports {Sck_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[1]}]
set_property PACKAGE_PIN N4 [get_ports {Ss_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[1]}]
set_property PACKAGE_PIN P1 [get_ports {SsFlash_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[1]}]
set_property PACKAGE_PIN N3 [get_ports {Mosi0_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[1]}]
set_property PACKAGE_PIN R2 [get_ports {Mosi1_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[1]}]
set_property PACKAGE_PIN N1 [get_ports {Mosi2_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[1]}]
set_property PACKAGE_PIN M2 [get_ports {Mosi3_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[1]}]
set_property PACKAGE_PIN P2 [get_ports {SpiRst_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[1]}]
set_property PACKAGE_PIN N11 [get_ports {Ld_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[1]}]



#SPI2
set_property PACKAGE_PIN E2 [get_ports {Sck_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[2]}]
set_property PACKAGE_PIN E1 [get_ports {Ss_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[2]}]
set_property PACKAGE_PIN F1 [get_ports {SsFlash_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[2]}]
set_property PACKAGE_PIN D1 [get_ports {Mosi0_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[2]}]
set_property PACKAGE_PIN D2 [get_ports {Mosi1_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[2]}]
set_property PACKAGE_PIN F2 [get_ports {Mosi2_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[2]}]
set_property PACKAGE_PIN G1 [get_ports {Mosi3_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[2]}]
set_property PACKAGE_PIN E3 [get_ports {SpiRst_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[2]}]
set_property PACKAGE_PIN N9 [get_ports {Ld_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[2]}]


#SPI3
set_property PACKAGE_PIN R10 [get_ports {Sck_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[3]}]
set_property PACKAGE_PIN P10 [get_ports {Ss_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[3]}]
set_property PACKAGE_PIN N10 [get_ports {SsFlash_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[3]}]
set_property PACKAGE_PIN N8 [get_ports {Mosi0_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[3]}]
set_property PACKAGE_PIN R8 [get_ports {Mosi1_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[3]}]
set_property PACKAGE_PIN R11 [get_ports {Mosi2_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[3]}]
set_property PACKAGE_PIN P11 [get_ports {Mosi3_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[3]}]
set_property PACKAGE_PIN R9 [get_ports {SpiRst_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[3]}]
set_property PACKAGE_PIN N13 [get_ports {Ld_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[3]}]




#SPI4
set_property PACKAGE_PIN R14 [get_ports {Sck_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[4]}]
set_property PACKAGE_PIN N14 [get_ports {Ss_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[4]}]
set_property PACKAGE_PIN P14 [get_ports {SsFlash_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[4]}]
set_property PACKAGE_PIN R13 [get_ports {Mosi0_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[4]}]
set_property PACKAGE_PIN P12 [get_ports {Mosi1_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[4]}]
set_property PACKAGE_PIN M15 [get_ports {Mosi2_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[4]}]
set_property PACKAGE_PIN M14 [get_ports {Mosi3_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[4]}]
set_property PACKAGE_PIN N15 [get_ports {SpiRst_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[4]}]
set_property PACKAGE_PIN P15 [get_ports {Ld_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[4]}]



#SPI5
set_property PACKAGE_PIN P6 [get_ports {Sck_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[5]}]
set_property PACKAGE_PIN R5 [get_ports {Ss_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[5]}]
set_property PACKAGE_PIN R6 [get_ports {SsFlash_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[5]}]
set_property PACKAGE_PIN R4 [get_ports {Mosi0_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[5]}]
set_property PACKAGE_PIN R3 [get_ports {Mosi1_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[5]}]
set_property PACKAGE_PIN N7 [get_ports {Mosi2_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[5]}]
set_property PACKAGE_PIN R7 [get_ports {Mosi3_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[5]}]
set_property PACKAGE_PIN N6 [get_ports {SpiRst_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[5]}]
set_property PACKAGE_PIN N12 [get_ports {Ld_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[5]}]


#SPI6
set_property PACKAGE_PIN B5 [get_ports {Sck_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sck_o[6]}]
set_property PACKAGE_PIN B3 [get_ports {Ss_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ss_o[6]}]
set_property PACKAGE_PIN A4 [get_ports {SsFlash_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SsFlash_o[6]}]
set_property PACKAGE_PIN B1 [get_ports {Mosi0_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi0_o[6]}]
set_property PACKAGE_PIN C4 [get_ports {Mosi1_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi1_o[6]}]
set_property PACKAGE_PIN B4 [get_ports {Mosi2_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi2_o[6]}]
set_property PACKAGE_PIN A3 [get_ports {Mosi3_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Mosi3_o[6]}]
set_property PACKAGE_PIN A2 [get_ports {SpiRst_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SpiRst_o[6]}]
set_property PACKAGE_PIN M8 [get_ports {Ld_i[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Ld_i[6]}]


set_property PACKAGE_PIN M7 [get_ports LD_o]
set_property IOSTANDARD LVCMOS33 [get_ports LD_o]

#==========================================================================
#	INPUT CLOCKS

set_property PACKAGE_PIN M10 [get_ports Clk123_i]
set_property IOSTANDARD LVCMOS33 [get_ports Clk123_i]
create_clock -period 8.130 -name Clk123_i -waveform {0.000 4.065} -add [get_ports Clk123_i]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk123_i_IBUF]
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets writeEn_i_IBUF]
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets readEn_i_IBUF]

























<<<<<<< HEAD


# set_multicycle_path -setup -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] 2
# set_multicycle_path -hold -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT0]] 2
# set_multicycle_path -setup -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] 2
# set_multicycle_path -hold -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT1]] 2
# set_multicycle_path -setup -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] 2
# set_multicycle_path -hold -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT2]] 2
# set_multicycle_path -setup -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] 2
# set_multicycle_path -hold -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT3]] 2
# set_multicycle_path -setup -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] 2
# set_multicycle_path -hold -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT4]] 2
# set_multicycle_path -setup -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] 3
# set_multicycle_path -hold -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT5]] 3
# set_multicycle_path -setup -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] 4
# set_multicycle_path -hold -from [get_clocks Clk123_i] -to [get_clocks -of_objects [get_pins MainMmcm/ClkDiv_inst/inst/mmcm_adv_inst/CLKOUT6]] 4
connect_debug_port u_ila_0/probe10 [get_nets [list toSpiData_0]]
=======
connect_debug_port u_ila_0/probe4 [get_nets [list {SpiGen[0].DataFifoWrapper/ToFifoData_i[0]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[1]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[2]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[3]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[4]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[5]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[6]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[7]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[16]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[17]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[18]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[19]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[20]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[21]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[22]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[23]}]]
connect_debug_port u_ila_0/probe5 [get_nets [list SmcAre_i_IBUF]]
connect_debug_port u_ila_0/probe7 [get_nets [list {SpiGen[0].QuadSPIm_inst/Start_i}]]
connect_debug_port u_ila_0/probe9 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoRdEn}]]
connect_debug_port u_ila_0/probe10 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoWrEn}]]
connect_debug_port u_ila_0/probe11 [get_nets [list {SpiGen[0].DataFifoWrapper/ToFifoVal_i}]]



>>>>>>> 12e27291e70fb6b3e69f84972965c9b6c964670e



create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list gclk]]
<<<<<<< HEAD
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0]
set_property port_width 16 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {SpiGen[0].DataFifoWrapper/ToFifoData_i[0]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[1]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[2]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[3]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[4]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[5]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[6]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[7]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[16]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[17]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[18]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[19]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[20]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[21]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[22]} {SpiGen[0].DataFifoWrapper/ToFifoData_i[23]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1]
set_property port_width 7 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {SpiTxRxEn[0]} {SpiTxRxEn[1]} {SpiTxRxEn[2]} {SpiTxRxEn[3]} {SpiTxRxEn[4]} {SpiTxRxEn[5]} {SpiTxRxEn[6]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe2]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {Mosi1_o_OBUF[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe3]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {Mosi2_o_OBUF[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe4]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {Mosi3_o_OBUF[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe5]
set_property port_width 11 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {toRegMapAddr[1]} {toRegMapAddr[2]} {toRegMapAddr[3]} {toRegMapAddr[4]} {toRegMapAddr[5]} {toRegMapAddr[6]} {toRegMapAddr[7]} {toRegMapAddr[8]} {toRegMapAddr[9]} {toRegMapAddr[10]} {toRegMapAddr[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe6]
set_property port_width 8 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {toRegMapData[0]} {toRegMapData[1]} {toRegMapData[2]} {toRegMapData[3]} {toRegMapData[4]} {toRegMapData[5]} {toRegMapData[6]} {toRegMapData[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe7]
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {toSpiData[0][31]} {toSpiData[0][30]} {toSpiData[0][29]} {toSpiData[0][28]} {toSpiData[0][27]} {toSpiData[0][26]} {toSpiData[0][25]} {toSpiData[0][24]} {toSpiData[0][23]} {toSpiData[0][22]} {toSpiData[0][21]} {toSpiData[0][20]} {toSpiData[0][19]} {toSpiData[0][18]} {toSpiData[0][17]} {toSpiData[0][16]} {toSpiData[0][15]} {toSpiData[0][14]} {toSpiData[0][13]} {toSpiData[0][12]} {toSpiData[0][11]} {toSpiData[0][10]} {toSpiData[0][9]} {toSpiData[0][8]} {toSpiData[0][7]} {toSpiData[0][6]} {toSpiData[0][5]} {toSpiData[0][4]} {toSpiData[0][3]} {toSpiData[0][2]} {toSpiData[0][1]} {toSpiData[0][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe8]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {SpiGen[0].DataFifoWrapper/emptyFlagTx}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {SpiGen[0].DataFifoWrapper/fullFlagTx}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list Mosi0Q_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list SmcAre_i_IBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list SmcAwe_i_IBUF]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {RegMap_inst/SpiTxRxEnReg[0]_i_1_n_0}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list SsQ_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {SpiGen[0].QuadSPIm_inst/Start_i}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list {SpiGen[0].DataFifoWrapper/ToFifoVal_i}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoRdEn}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {SpiGen[0].DataFifoWrapper/txFifoWrEn}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list valToTxQ_0]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list toRegMapVal]]
=======
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {smcData[0]} {smcData[1]} {smcData[2]} {smcData[3]} {smcData[4]} {smcData[5]} {smcData[6]} {smcData[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 7 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {toFifoVal[0]} {toFifoVal[1]} {toFifoVal[2]} {toFifoVal[3]} {toFifoVal[4]} {toFifoVal[5]} {toFifoVal[6]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {toRegMapData[0]} {toRegMapData[1]} {toRegMapData[2]} {toRegMapData[3]} {toRegMapData[4]} {toRegMapData[5]} {toRegMapData[6]} {toRegMapData[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 11 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {toRegMapAddr[1]} {toRegMapAddr[2]} {toRegMapAddr[3]} {toRegMapAddr[4]} {toRegMapAddr[5]} {toRegMapAddr[6]} {toRegMapAddr[7]} {toRegMapAddr[8]} {toRegMapAddr[9]} {toRegMapAddr[10]} {toRegMapAddr[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 11 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {smcAddr[1]} {smcAddr[2]} {smcAddr[3]} {smcAddr[4]} {smcAddr[5]} {smcAddr[6]} {smcAddr[7]} {smcAddr[8]} {smcAddr[9]} {smcAddr[10]} {smcAddr[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 112 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {toFifoData[0]} {toFifoData[1]} {toFifoData[2]} {toFifoData[3]} {toFifoData[4]} {toFifoData[5]} {toFifoData[6]} {toFifoData[7]} {toFifoData[16]} {toFifoData[17]} {toFifoData[18]} {toFifoData[19]} {toFifoData[20]} {toFifoData[21]} {toFifoData[22]} {toFifoData[23]} {toFifoData[32]} {toFifoData[33]} {toFifoData[34]} {toFifoData[35]} {toFifoData[36]} {toFifoData[37]} {toFifoData[38]} {toFifoData[39]} {toFifoData[48]} {toFifoData[49]} {toFifoData[50]} {toFifoData[51]} {toFifoData[52]} {toFifoData[53]} {toFifoData[54]} {toFifoData[55]} {toFifoData[64]} {toFifoData[65]} {toFifoData[66]} {toFifoData[67]} {toFifoData[68]} {toFifoData[69]} {toFifoData[70]} {toFifoData[71]} {toFifoData[80]} {toFifoData[81]} {toFifoData[82]} {toFifoData[83]} {toFifoData[84]} {toFifoData[85]} {toFifoData[86]} {toFifoData[87]} {toFifoData[96]} {toFifoData[97]} {toFifoData[98]} {toFifoData[99]} {toFifoData[100]} {toFifoData[101]} {toFifoData[102]} {toFifoData[103]} {toFifoData[112]} {toFifoData[113]} {toFifoData[114]} {toFifoData[115]} {toFifoData[116]} {toFifoData[117]} {toFifoData[118]} {toFifoData[119]} {toFifoData[128]} {toFifoData[129]} {toFifoData[130]} {toFifoData[131]} {toFifoData[132]} {toFifoData[133]} {toFifoData[134]} {toFifoData[135]} {toFifoData[144]} {toFifoData[145]} {toFifoData[146]} {toFifoData[147]} {toFifoData[148]} {toFifoData[149]} {toFifoData[150]} {toFifoData[151]} {toFifoData[160]} {toFifoData[161]} {toFifoData[162]} {toFifoData[163]} {toFifoData[164]} {toFifoData[165]} {toFifoData[166]} {toFifoData[167]} {toFifoData[176]} {toFifoData[177]} {toFifoData[178]} {toFifoData[179]} {toFifoData[180]} {toFifoData[181]} {toFifoData[182]} {toFifoData[183]} {toFifoData[192]} {toFifoData[193]} {toFifoData[194]} {toFifoData[195]} {toFifoData[196]} {toFifoData[197]} {toFifoData[198]} {toFifoData[199]} {toFifoData[208]} {toFifoData[209]} {toFifoData[210]} {toFifoData[211]} {toFifoData[212]} {toFifoData[213]} {toFifoData[214]} {toFifoData[215]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list smcVal]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list toRegMapVal]]
>>>>>>> 12e27291e70fb6b3e69f84972965c9b6c964670e
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets gclk]