S5443_V3/sources_1/new/RegMap/RegMap.v

//////////////////////////////////////////////////////////////////////////////////
// Company:			TAIR
// Engineer:		
// 
// Create Date:		10/30/2023 11:24:31 AM
// Design Name:
// Module Name:		RegMap
// Project Name:	S5443_V3_FPGA3
// Target Devices:	BOARD: BY5443v3. FPGA: xc7s25csga225-2
// Tool Versions:
// Description: 	
// 
// Dependencies: 
// 
// Revision:
// Revision 1.0 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module RegMap #(
	parameter CMD_REG_WIDTH = 32,
	parameter ADDR_REG_WIDTH = 12
)
(
	input Clk_i,
	input Rst_i,
	input [1:0] SmcBe_i,

	input [CMD_REG_WIDTH/2-1:0] Data_i,
	input [ADDR_REG_WIDTH-1:0] Addr_i,
	input Val_i,

	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg0_i,
	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg0_i,
	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg1_i,
	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg1_i,
	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg2_i,
	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg2_i,
	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg3_i,
	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg3_i,
	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg4_i,
	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg4_i,
	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg5_i,
	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg5_i,
	input [CMD_REG_WIDTH-1:0] TxFifoCtrlReg6_i,
	input [CMD_REG_WIDTH-1:0] RxFifoCtrlReg6_i,

	input [6:0] LdReg_i,

	output reg [CMD_REG_WIDTH/2-1:0] Spi0CtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi0ClkReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi0CsDelayReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi0CsCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi0TxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi0RxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi0TxFifoReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi0RxFifoReg_o,

	output reg [CMD_REG_WIDTH/2-1:0] Spi1CtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi1ClkReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi1CsDelayReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi1CsCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi1TxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi1RxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi1TxFifoReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi1RxFifoReg_o,

	output reg [CMD_REG_WIDTH/2-1:0] Spi2CtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi2ClkReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi2CsDelayReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi2CsCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi2TxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi2RxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi2TxFifoReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi2RxFifoReg_o,
	
	output reg [CMD_REG_WIDTH/2-1:0] Spi3CtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi3ClkReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi3CsDelayReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi3CsCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi3TxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi3RxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi3TxFifoReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi3RxFifoReg_o,

	output reg [CMD_REG_WIDTH/2-1:0] Spi4CtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi4ClkReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi4CsDelayReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi4CsCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi4TxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi4RxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi4TxFifoReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi4RxFifoReg_o,
	
	output reg [CMD_REG_WIDTH/2-1:0] Spi5CtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi5ClkReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi5CsDelayReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi5CsCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi5TxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi5RxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi5TxFifoReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi5RxFifoReg_o,

	output reg [CMD_REG_WIDTH/2-1:0] Spi6CtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi6ClkReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi6CsDelayReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi6CsCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi6TxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi6RxFifoCtrlReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi6TxFifoReg_o,
	output reg [CMD_REG_WIDTH/2-1:0] Spi6RxFifoReg_o,

	output [CMD_REG_WIDTH/2-1:0] SpiTxRxEnReg_o,
	output [CMD_REG_WIDTH-1:0] GPIOAReg_o,

	output [CMD_REG_WIDTH/2-1:0] AnsDataReg_o,
	
	output Led_o
);

//================================================================================
//	REG/WIRE
//================================================================================
	(* dont_touch = "yes" *)reg [CMD_REG_WIDTH/2-1:0] spiTxRxEnReg;
	reg [CMD_REG_WIDTH/2-1:0] GPIOAReg;
	reg [CMD_REG_WIDTH/2-1:0] GPIOARegS;
	
	(* dont_touch = "yes" *)reg [CMD_REG_WIDTH/2-1:0] ansReg;
	(* dont_touch = "yes" *)reg [CMD_REG_WIDTH/2-1:0] ledReg;
	
	reg	[1:0]	beReg;

//================================================================================
//	ASSIGNMENTS
//================================================================================
	assign SpiTxRxEnReg_o = spiTxRxEnReg;
	assign GPIOAReg_o = {GPIOARegS, GPIOAReg};
	
	assign AnsDataReg_o = ansReg;
	assign Led_o = ledReg[0];

//================================================================================
//	LOCALPARAMS
//================================================================================
	localparam SPI_0_CTRL_ADDR 				= 12'h00;
	localparam SPI_0_CLK_ADDR  				= 12'h04;
	localparam SPI_0_CS_DELAY_ADDR 			= 12'h08;
	localparam SPI_0_CS_CTRL_ADDR 			= 12'h0c;
	localparam SPI_0_TX_FIFO_CTRL_ADDR_LSB 	= 12'h10;
	localparam SPI_0_TX_FIFO_CTRL_ADDR_MSB 	= 12'h12;
	localparam SPI_0_RX_FIFO_CTRL_ADDR_LSB 	= 12'h14;
	localparam SPI_0_RX_FIFO_CTRL_ADDR_MSB 	= 12'h16;
	localparam SPI_0_TX_FIFO 				= 12'h18;
	localparam SPI_0_RX_FIFO 				= 12'h1c;
	
	localparam SPI_1_CTRL_ADDR 				= 12'h50;
	localparam SPI_1_CLK_ADDR  				= 12'h54;
	localparam SPI_1_CS_DELAY_ADDR 			= 12'h58;
	localparam SPI_1_CS_CTRL_ADDR 			= 12'h5c;
	localparam SPI_1_TX_FIFO_CTRL_ADDR_LSB 	= 12'h60;
	localparam SPI_1_TX_FIFO_CTRL_ADDR_MSB 	= 12'h62;
	localparam SPI_1_RX_FIFO_CTRL_ADDR_LSB 	= 12'h64;
	localparam SPI_1_RX_FIFO_CTRL_ADDR_MSB 	= 12'h66;
	localparam SPI_1_TX_FIFO 				= 12'h68;
	localparam SPI_1_RX_FIFO 				= 12'h6c;
	
	localparam SPI_2_CTRL_ADDR 				= 12'hF0;
	localparam SPI_2_CLK_ADDR  				= 12'hF4;
	localparam SPI_2_CS_DELAY_ADDR 			= 12'hF8;
	localparam SPI_2_CS_CTRL_ADDR 			= 12'hFc;
	localparam SPI_2_TX_FIFO_CTRL_ADDR_LSB 	= 12'h100;
	localparam SPI_2_TX_FIFO_CTRL_ADDR_MSB 	= 12'h102;
	localparam SPI_2_RX_FIFO_CTRL_ADDR_LSB 	= 12'h104;
	localparam SPI_2_RX_FIFO_CTRL_ADDR_MSB 	= 12'h106;
	localparam SPI_2_TX_FIFO 				= 12'h108;
	localparam SPI_2_RX_FIFO 				= 12'h10c;
	
	localparam SPI_3_CTRL_ADDR 				= 12'h140;
	localparam SPI_3_CLK_ADDR  				= 12'h144;
	localparam SPI_3_CS_DELAY_ADDR 			= 12'h148;
	localparam SPI_3_CS_CTRL_ADDR 			= 12'h14c;
	localparam SPI_3_TX_FIFO_CTRL_ADDR_LSB 	= 12'h150;
	localparam SPI_3_TX_FIFO_CTRL_ADDR_MSB 	= 12'h152;
	localparam SPI_3_RX_FIFO_CTRL_ADDR_LSB 	= 12'h154;
	localparam SPI_3_RX_FIFO_CTRL_ADDR_MSB 	= 12'h156;
	localparam SPI_3_TX_FIFO 				= 12'h158;
	localparam SPI_3_RX_FIFO 				= 12'h15c;
	
	localparam SPI_4_CTRL_ADDR 				= 12'h190;
	localparam SPI_4_CLK_ADDR  				= 12'h194;
	localparam SPI_4_CS_DELAY_ADDR 			= 12'h198;
	localparam SPI_4_CS_CTRL_ADDR 			= 12'h19c;
	localparam SPI_4_TX_FIFO_CTRL_ADDR_LSB 	= 12'h1a0;
	localparam SPI_4_TX_FIFO_CTRL_ADDR_MSB 	= 12'h1a2;
	localparam SPI_4_RX_FIFO_CTRL_ADDR_LSB 	= 12'h1a4;
	localparam SPI_4_RX_FIFO_CTRL_ADDR_MSB 	= 12'h1a6;
	localparam SPI_4_TX_FIFO 				= 12'h1a8;
	localparam SPI_4_RX_FIFO 				= 12'h1ac;
	
	localparam SPI_5_CTRL_ADDR 				= 12'h1e0;
	localparam SPI_5_CLK_ADDR  				= 12'h1e4;
	localparam SPI_5_CS_DELAY_ADDR 			= 12'h1e8;
	localparam SPI_5_CS_CTRL_ADDR 			= 12'h1ec;
	localparam SPI_5_TX_FIFO_CTRL_ADDR_LSB 	= 12'h1f0;
	localparam SPI_5_TX_FIFO_CTRL_ADDR_MSB 	= 12'h1f2;
	localparam SPI_5_RX_FIFO_CTRL_ADDR_LSB 	= 12'h1f4;
	localparam SPI_5_RX_FIFO_CTRL_ADDR_MSB 	= 12'h1f6;
	localparam SPI_5_TX_FIFO 				= 12'h1f8;
	localparam SPI_5_RX_FIFO 				= 12'h1fc;
	
	localparam SPI_6_CTRL_ADDR 				= 12'h230;
	localparam SPI_6_CLK_ADDR  				= 12'h234;
	localparam SPI_6_CS_DELAY_ADDR 			= 12'h238;
	localparam SPI_6_CS_CTRL_ADDR 			= 12'h23c;
	localparam SPI_6_TX_FIFO_CTRL_ADDR_LSB 	= 12'h240;
	localparam SPI_6_TX_FIFO_CTRL_ADDR_MSB 	= 12'h242;
	localparam SPI_6_RX_FIFO_CTRL_ADDR_LSB 	= 12'h244;
	localparam SPI_6_RX_FIFO_CTRL_ADDR_MSB 	= 12'h246;
	localparam SPI_6_TX_FIFO 				= 12'h248;
	localparam SPI_6_RX_FIFO 				= 12'h24c;
	
	localparam SPI_TX_RX_EN 	= 12'hF00;
	localparam GPIO_CTRL_ADDR 	= 12'hFF0;
	localparam GPIO_CTRL_ADDR_S = 12'hFF2;
	
	localparam DEBUG_0_ADDR = 12'hFF8;
	localparam DEBUG_1_ADDR = 12'hFFC;

//================================================================================
//  CODING
//================================================================================
	always	@(posedge	Clk_i)	begin
		if	(!Rst_i)	begin
			beReg	<=	2'b0;
		end	else	begin
			beReg	<=	SmcBe_i;
		end
	end
	
	always @(posedge Clk_i) begin 
		if (Rst_i) begin 
			Spi0ClkReg_o 		<= 0;
			Spi0CtrlReg_o 		<= 0;
			Spi0CsDelayReg_o 	<= 0;
			Spi0CsCtrlReg_o 	<= 0;
			Spi0TxFifoCtrlReg_o <= 0;
			Spi0RxFifoCtrlReg_o <= 0;
			Spi1ClkReg_o 		<= 0;
			Spi1CtrlReg_o 		<= 0;
			Spi1CsDelayReg_o 	<= 0;
			Spi1CsCtrlReg_o 	<= 0;
			Spi1TxFifoCtrlReg_o <= 0;
			Spi1RxFifoCtrlReg_o <= 0;
			Spi2ClkReg_o 		<= 0;
			Spi2CtrlReg_o 		<= 0;
			Spi2CsDelayReg_o 	<= 0;
			Spi2CsCtrlReg_o 	<= 0;
			Spi2TxFifoCtrlReg_o <= 0;
			Spi2RxFifoCtrlReg_o <= 0;
			Spi3ClkReg_o 		<= 0;
			Spi3CtrlReg_o 		<= 0;
			Spi3CsDelayReg_o 	<= 0;
			Spi3CsCtrlReg_o 	<= 0;
			Spi3TxFifoCtrlReg_o <= 0;
			Spi3RxFifoCtrlReg_o <= 0;
			Spi4ClkReg_o 		<= 0;
			Spi4CtrlReg_o 		<= 0;
			Spi4CsDelayReg_o 	<= 0;
			Spi4CsCtrlReg_o 	<= 0;
			Spi4TxFifoCtrlReg_o <= 0;
			Spi4RxFifoCtrlReg_o <= 0;
			Spi5ClkReg_o 		<= 0;
			Spi5CtrlReg_o 		<= 0;
			Spi5CsDelayReg_o 	<= 0;
			Spi5CsCtrlReg_o 	<= 0;
			Spi5TxFifoCtrlReg_o <= 0;
			Spi5RxFifoCtrlReg_o <= 0;
			Spi6ClkReg_o 		<= 0;
			Spi6CtrlReg_o 		<= 0;
			Spi6CsDelayReg_o 	<= 0;
			Spi6CsCtrlReg_o 	<= 0;
			Spi6TxFifoCtrlReg_o <= 0;
			Spi6RxFifoCtrlReg_o <= 0;
			spiTxRxEnReg 		<= 0;
			GPIOAReg 			<= 0;
			GPIOARegS 			<= 0;
			ledReg 				<= 0;
		end
		else begin 
			if (Val_i) begin 
				case (beReg)  
					0 : begin 
						case (Addr_i) 
							SPI_0_CTRL_ADDR : begin 
								Spi0CtrlReg_o <= Data_i;
							end
							SPI_0_CLK_ADDR : begin 
								Spi0ClkReg_o <= Data_i;
							end
							SPI_0_CS_DELAY_ADDR : begin 
								Spi0CsDelayReg_o <= Data_i;
							end
							SPI_0_CS_CTRL_ADDR : begin 
								Spi0CsCtrlReg_o <= Data_i;
							end
							SPI_0_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi0TxFifoCtrlReg_o <= Data_i;
							end
							SPI_0_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi0RxFifoCtrlReg_o <= Data_i;
							end
							SPI_1_CTRL_ADDR : begin 
								Spi1CtrlReg_o <= Data_i;
							end
							SPI_1_CLK_ADDR : begin 
								Spi1ClkReg_o <= Data_i;
							end
							SPI_1_CS_DELAY_ADDR : begin 
								Spi1CsDelayReg_o <= Data_i;
							end
							SPI_1_CS_CTRL_ADDR : begin 
								Spi1CsCtrlReg_o <= Data_i;
							end
							SPI_1_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi1TxFifoCtrlReg_o <= Data_i;
							end
							SPI_1_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi1RxFifoCtrlReg_o <= Data_i;
							end
							SPI_2_CTRL_ADDR : begin 
								Spi2CtrlReg_o <= Data_i;
							end
							SPI_2_CLK_ADDR : begin 
								Spi2ClkReg_o <= Data_i;
							end
							SPI_2_CS_DELAY_ADDR : begin 
								Spi2CsDelayReg_o <= Data_i;
							end
							SPI_2_CS_CTRL_ADDR : begin 
								Spi2CsCtrlReg_o <= Data_i;
							end
							SPI_2_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi2TxFifoCtrlReg_o <= Data_i;
							end
							SPI_2_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi2RxFifoCtrlReg_o <= Data_i;
							end
							SPI_3_CTRL_ADDR : begin 
								Spi3CtrlReg_o <= Data_i;
							end
							SPI_3_CLK_ADDR : begin 
								Spi3ClkReg_o <= Data_i;
							end
							SPI_3_CS_DELAY_ADDR : begin 
								Spi3CsDelayReg_o <= Data_i;
							end
							SPI_3_CS_CTRL_ADDR : begin 
								Spi3CsCtrlReg_o <= Data_i;
							end
							SPI_3_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi3TxFifoCtrlReg_o <= Data_i;
							end
							SPI_3_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi3RxFifoCtrlReg_o <= Data_i;
							end
							SPI_4_CTRL_ADDR : begin 
								Spi4CtrlReg_o <= Data_i;
							end
							SPI_4_CLK_ADDR : begin 
								Spi4ClkReg_o <= Data_i;
							end
							SPI_4_CS_DELAY_ADDR : begin 
								Spi4CsDelayReg_o <= Data_i;
							end
							SPI_4_CS_CTRL_ADDR : begin 
								Spi4CsCtrlReg_o <= Data_i;
							end
							SPI_4_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi4TxFifoCtrlReg_o <= Data_i;
							end
							SPI_4_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi4RxFifoCtrlReg_o <= Data_i;
							end
							SPI_5_CTRL_ADDR : begin 
								Spi5CtrlReg_o <= Data_i;
							end
							SPI_5_CLK_ADDR : begin 
								Spi5ClkReg_o <= Data_i;
							end
							SPI_5_CS_DELAY_ADDR : begin 
								Spi5CsDelayReg_o <= Data_i;
							end
							SPI_5_CS_CTRL_ADDR : begin 
								Spi5CsCtrlReg_o <= Data_i;
							end
							SPI_5_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi5TxFifoCtrlReg_o <= Data_i;
							end
							SPI_5_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi5RxFifoCtrlReg_o <= Data_i;
							end
							SPI_6_CTRL_ADDR : begin 
								Spi6CtrlReg_o <= Data_i;
							end
							SPI_6_CLK_ADDR : begin 
								Spi6ClkReg_o <= Data_i;
							end
							SPI_6_CS_DELAY_ADDR : begin 
								Spi6CsDelayReg_o <= Data_i;
							end
							SPI_6_CS_CTRL_ADDR : begin 
								Spi6CsCtrlReg_o <= Data_i;
							end
							SPI_6_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi6TxFifoCtrlReg_o <= Data_i;
							end
							SPI_6_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi6RxFifoCtrlReg_o <= Data_i;
							end
							SPI_TX_RX_EN : begin 
								spiTxRxEnReg <= Data_i;
							end
							GPIO_CTRL_ADDR : begin 
								GPIOAReg <= Data_i;
							end
							GPIO_CTRL_ADDR_S : begin 
								GPIOARegS <= Data_i;
							end
							DEBUG_0_ADDR : begin 
								ledReg <= Data_i;
							end
						endcase
					end
					1 : begin 
						case (Addr_i)
							SPI_0_CTRL_ADDR : begin
								Spi0CtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_0_CLK_ADDR : begin 
								Spi0ClkReg_o[15:8] <= Data_i[15:8];
							end
							SPI_0_CS_DELAY_ADDR : begin 
								Spi0CsDelayReg_o[15:8] <= Data_i[15:8];
							end
							SPI_0_CS_CTRL_ADDR : begin 
								Spi0CsCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_0_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi0TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_0_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi0RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_1_CTRL_ADDR : begin 
								Spi1CtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_1_CLK_ADDR : begin 
								Spi1ClkReg_o[15:8] <= Data_i[15:8];
							end
							SPI_1_CS_DELAY_ADDR : begin 
								Spi1CsDelayReg_o[15:8] <= Data_i[15:8];
							end
							SPI_1_CS_CTRL_ADDR : begin 
								Spi1CsCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_1_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi1TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_1_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi1RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_2_CTRL_ADDR : begin 
								Spi2CtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_2_CLK_ADDR : begin 
								Spi2ClkReg_o[15:8] <= Data_i[15:8];
							end
							SPI_2_CS_DELAY_ADDR : begin 
								Spi2CsDelayReg_o[15:8] <= Data_i[15:8];
							end
							SPI_2_CS_CTRL_ADDR : begin 
								Spi2CsCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_2_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi2TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_2_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi2RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_3_CTRL_ADDR : begin 
								Spi3CtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_3_CLK_ADDR : begin 
								Spi3ClkReg_o[15:8] <= Data_i[15:8];
							end
							SPI_3_CS_DELAY_ADDR : begin 
								Spi3CsDelayReg_o[15:8] <= Data_i[15:8];
							end
							SPI_3_CS_CTRL_ADDR : begin 
								Spi3CsCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_3_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi3TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_3_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi3RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_4_CTRL_ADDR : begin 
								Spi4CtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_4_CLK_ADDR : begin 
								Spi4ClkReg_o[15:8] <= Data_i[15:8];
							end
							SPI_4_CS_DELAY_ADDR : begin 
								Spi4CsDelayReg_o[15:8] <= Data_i[15:8];
							end
							SPI_4_CS_CTRL_ADDR : begin 
								Spi4CsCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_4_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi4TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_4_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi4RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_5_CTRL_ADDR : begin 
								Spi5CtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_5_CLK_ADDR : begin 
								Spi5ClkReg_o[15:8] <= Data_i[15:8];
							end
							SPI_5_CS_DELAY_ADDR : begin 
								Spi5CsDelayReg_o[15:8] <= Data_i[15:8];
							end
							SPI_5_CS_CTRL_ADDR : begin 
								Spi5CsCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_5_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi5TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_5_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi5RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_6_CTRL_ADDR : begin 
								Spi6CtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_6_CLK_ADDR : begin 
								Spi6ClkReg_o[15:8] <= Data_i[15:8];
							end
							SPI_6_CS_DELAY_ADDR : begin 
								Spi6CsDelayReg_o[15:8] <= Data_i[15:8];
							end
							SPI_6_CS_CTRL_ADDR : begin 
								Spi6CsCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_6_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi6TxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_6_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi6RxFifoCtrlReg_o[15:8] <= Data_i[15:8];
							end
							SPI_TX_RX_EN : begin 
								spiTxRxEnReg[15:8] <= Data_i[15:8];
							end
							GPIO_CTRL_ADDR : begin 
								GPIOAReg[15:8] <= Data_i[15:8];
							end
							GPIO_CTRL_ADDR_S : begin 
								GPIOARegS[15:8] <= Data_i[15:8];
							end
							DEBUG_0_ADDR : begin 
								ledReg[15:8] <= Data_i[15:8];
							end
						endcase 
					end
					2 : begin 
						case (Addr_i) 
							SPI_0_CTRL_ADDR : begin 
								Spi0CtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_0_CLK_ADDR : begin 
								Spi0ClkReg_o[7:0] <= Data_i[7:0];
							end
							SPI_0_CS_DELAY_ADDR : begin 
								Spi0CsDelayReg_o[7:0] <= Data_i[7:0];
							end
							SPI_0_CS_CTRL_ADDR : begin 
								Spi0CsCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_0_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi0TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_0_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi0RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_1_CTRL_ADDR : begin 
								Spi1CtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_1_CLK_ADDR : begin 
								Spi1ClkReg_o[7:0] <= Data_i[7:0];
							end
							SPI_1_CS_DELAY_ADDR : begin 
								Spi1CsDelayReg_o[7:0] <= Data_i[7:0];
							end
							SPI_1_CS_CTRL_ADDR : begin 
								Spi1CsCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_1_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi1TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_1_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi1RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_2_CTRL_ADDR : begin 
								Spi2CtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_2_CLK_ADDR : begin 
								Spi2ClkReg_o[7:0] <= Data_i[7:0];
							end
							SPI_2_CS_DELAY_ADDR : begin 
								Spi2CsDelayReg_o[7:0] <= Data_i[7:0];
							end
							SPI_2_CS_CTRL_ADDR : begin 
								Spi2CsCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_2_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi2TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_2_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi2RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_3_CTRL_ADDR : begin 
								Spi3CtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_3_CLK_ADDR : begin 
								Spi3ClkReg_o[7:0] <= Data_i[7:0];
							end
							SPI_3_CS_DELAY_ADDR : begin 
								Spi3CsDelayReg_o[7:0] <= Data_i[7:0];
							end
							SPI_3_CS_CTRL_ADDR : begin 
								Spi3CsCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_3_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi3TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_3_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi3RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_4_CTRL_ADDR : begin 
								Spi4CtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_4_CLK_ADDR : begin 
								Spi4ClkReg_o[7:0] <= Data_i[7:0];
							end
							SPI_4_CS_DELAY_ADDR : begin 
								Spi4CsDelayReg_o[7:0] <= Data_i[7:0];
							end
							SPI_4_CS_CTRL_ADDR : begin 
								Spi4CsCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_4_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi4TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_4_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi4RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_5_CTRL_ADDR : begin 
								Spi5CtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_5_CLK_ADDR : begin 
								Spi5ClkReg_o[7:0] <= Data_i[7:0];
							end
							SPI_5_CS_DELAY_ADDR : begin 
								Spi5CsDelayReg_o[7:0] <= Data_i[7:0];
							end
							SPI_5_CS_CTRL_ADDR : begin 
								Spi5CsCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_5_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi5TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_5_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi5RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_6_CTRL_ADDR : begin 
								Spi6CtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_6_CLK_ADDR : begin 
								Spi6ClkReg_o[7:0] <= Data_i[7:0];
							end
							SPI_6_CS_DELAY_ADDR : begin 
								Spi6CsDelayReg_o[7:0] <= Data_i[7:0];
							end
							SPI_6_CS_CTRL_ADDR : begin 
								Spi6CsCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_6_TX_FIFO_CTRL_ADDR_LSB : begin 
								Spi6TxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_6_RX_FIFO_CTRL_ADDR_LSB : begin 
								Spi6RxFifoCtrlReg_o[7:0] <= Data_i[7:0];
							end
							SPI_TX_RX_EN : begin 
								spiTxRxEnReg[7:0] <= Data_i[7:0];
							end
							GPIO_CTRL_ADDR : begin 
								GPIOAReg[7:0] <= Data_i[7:0];
							end
							GPIO_CTRL_ADDR_S : begin 
								GPIOARegS[7:0] <= Data_i[7:0];
							end
							DEBUG_0_ADDR : begin 
								ledReg[7:0] <= Data_i[7:0];
							end
						endcase
					end
				endcase
			end
		end
	end
	
	always @(*) begin 
		if (Rst_i) begin 
			ansReg = 0;
		end	else begin
			case (Addr_i)
				SPI_0_CTRL_ADDR : begin 
					ansReg = Spi0CtrlReg_o;
				end
				SPI_0_CLK_ADDR : begin 
					ansReg = Spi0ClkReg_o;
				end
				SPI_0_CS_DELAY_ADDR : begin 
					ansReg = Spi0CsDelayReg_o;
				end
				SPI_0_CS_CTRL_ADDR : begin 
					ansReg = Spi0CsCtrlReg_o;
				end
				SPI_0_TX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = TxFifoCtrlReg0_i[15:0];
				end
				SPI_0_TX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = TxFifoCtrlReg0_i[31:16];
				end
				SPI_0_RX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = RxFifoCtrlReg0_i[15:0];
				end
				SPI_0_RX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = RxFifoCtrlReg0_i[31:16];
				end
				SPI_1_CTRL_ADDR : begin 
					ansReg = Spi1CtrlReg_o;
				end
				SPI_1_CLK_ADDR : begin 
					ansReg = Spi1ClkReg_o;
				end
				SPI_1_CS_DELAY_ADDR : begin 
					ansReg = Spi1CsDelayReg_o;
				end
				SPI_1_CS_CTRL_ADDR : begin 
					ansReg = Spi1CsCtrlReg_o;
				end
				SPI_1_TX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = TxFifoCtrlReg1_i[15:0];
				end
				SPI_1_TX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = TxFifoCtrlReg1_i[31:16];
				end
				SPI_1_RX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = RxFifoCtrlReg1_i[15:0];
				end
				SPI_1_RX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = RxFifoCtrlReg1_i[31:16];
				end
				SPI_2_CTRL_ADDR : begin 
					ansReg = Spi2CtrlReg_o;
				end
				SPI_2_CLK_ADDR : begin 
					ansReg = Spi2ClkReg_o;
				end
				SPI_2_CS_DELAY_ADDR : begin 
					ansReg = Spi2CsDelayReg_o;
				end
				SPI_2_CS_CTRL_ADDR : begin 
					ansReg = Spi2CsCtrlReg_o;
				end
				SPI_2_TX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = TxFifoCtrlReg2_i[15:0];
				end
				SPI_2_TX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = TxFifoCtrlReg2_i[31:16];
				end
				SPI_2_RX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = RxFifoCtrlReg2_i[15:0];
				end
				SPI_2_RX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = RxFifoCtrlReg2_i[31:16];
				end
				SPI_3_CTRL_ADDR : begin 
					ansReg = Spi3CtrlReg_o;
				end
				SPI_3_CLK_ADDR : begin 
					ansReg = Spi3ClkReg_o;
				end
				SPI_3_CS_DELAY_ADDR : begin 
					ansReg = Spi3CsDelayReg_o;
				end
				SPI_3_CS_CTRL_ADDR : begin 
					ansReg = Spi3CsCtrlReg_o;
				end
				SPI_3_TX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = TxFifoCtrlReg3_i[15:0];
				end
				SPI_3_TX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = TxFifoCtrlReg3_i[31:16];
				end
				SPI_3_RX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = RxFifoCtrlReg3_i[15:0];
				end
				SPI_3_RX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = RxFifoCtrlReg3_i[31:16];
				end
				SPI_4_CTRL_ADDR : begin 
					ansReg = Spi4CtrlReg_o;
				end
				SPI_4_CLK_ADDR : begin 
					ansReg = Spi4ClkReg_o;
				end
				SPI_4_CS_DELAY_ADDR : begin 
					ansReg = Spi4CsDelayReg_o;
				end
				SPI_4_CS_CTRL_ADDR : begin 
					ansReg = Spi4CsCtrlReg_o;
				end
				SPI_4_TX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = TxFifoCtrlReg4_i[15:0];
				end
				SPI_4_TX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = TxFifoCtrlReg4_i[31:16];
				end
				SPI_4_RX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = RxFifoCtrlReg4_i[15:0];
				end
				SPI_4_RX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = RxFifoCtrlReg4_i[31:16];
				end
				SPI_5_CTRL_ADDR : begin 
					ansReg = Spi5CtrlReg_o;
				end
				SPI_5_CLK_ADDR : begin 
					ansReg = Spi5ClkReg_o;
				end
				SPI_5_CS_DELAY_ADDR : begin 
					ansReg = Spi5CsDelayReg_o;
				end
				SPI_5_CS_CTRL_ADDR : begin 
					ansReg = Spi5CsCtrlReg_o;
				end
				SPI_5_TX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = TxFifoCtrlReg5_i[15:0];
				end
				SPI_5_TX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = TxFifoCtrlReg5_i[31:16];
				end
				SPI_5_RX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = RxFifoCtrlReg5_i[15:0];
				end
				SPI_5_RX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = RxFifoCtrlReg5_i[31:16];
				end
				SPI_6_CTRL_ADDR : begin 
					ansReg = Spi6CtrlReg_o;
				end
				SPI_6_CLK_ADDR : begin 
					ansReg = Spi6ClkReg_o;
				end
				SPI_6_CS_DELAY_ADDR : begin 
					ansReg = Spi6CsDelayReg_o;
				end
				SPI_6_CS_CTRL_ADDR : begin 
					ansReg = Spi6CsCtrlReg_o;
				end
				SPI_6_TX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = TxFifoCtrlReg6_i[15:0];
				end
				SPI_6_TX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = TxFifoCtrlReg6_i[31:16];
				end
				SPI_6_RX_FIFO_CTRL_ADDR_LSB : begin 
					ansReg = RxFifoCtrlReg6_i[15:0];
				end
				SPI_6_RX_FIFO_CTRL_ADDR_MSB : begin 
					ansReg = RxFifoCtrlReg6_i[31:16];
				end
				SPI_TX_RX_EN : begin 
					ansReg = spiTxRxEnReg;
				end
				GPIO_CTRL_ADDR : begin 
					ansReg = GPIOAReg;
				end
				GPIO_CTRL_ADDR_S : begin 
					ansReg = {9'd0,LdReg_i};
				end
				DEBUG_0_ADDR : begin 
					ansReg = ledReg;
				end
				default : begin 
					ansReg = 0;
				end
			endcase
		end
	end

endmodule