S5443_V3/sources_1/new/DataFifo/TxFifoPtrsync.v

module TxFifoPtrSync #(
    parameter WIDTH = 8,
    parameter STAGES = 3



)
(
    input ClkFast_i,
    input ClkSlow_i,
    input [WIDTH-1:0] TxFifoWrPtr_i,

    output [WIDTH-1:0] TxFifoWrPtr_o
);

//lauch registers 
reg [WIDTH-1:0] txFifoWrPtrReg;


// capture registers
(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] txFifoWrPtrReg_c;



assign TxFifoWrPtr_o = txFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];


always @(posedge ClkFast_i) begin
    txFifoWrPtrReg <= TxFifoWrPtr_i;
end





always @(posedge ClkSlow_i) begin
    txFifoWrPtrReg_c <= {txFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], txFifoWrPtrReg};
end





endmodule