S5443_V3/sources_1/new/MMCM/ClkGen_tb.v

`timescale 1ns / 1ps
module ClkGen_tb();






reg Clk_i;
reg Rst_i;

reg [3:0] clkDiv_i;






always #(1.667/2) Clk_i = ~Clk_i;




ClkGenGowin ClkGen_inst (
    .Clk_i(Clk_i), 
    .Rst_i(Rst_i), 
    .Clk75_o(),
    .Clk40_o(),
    .Clk30_o(),
    .Clk5_o()
);



initial begin 
    Clk_i = 0;
    Rst_i = 1;
    clkDiv_i = 3;
    #1000;
    Rst_i = 0;

end




endmodule