S5443_V3/sources_1/new/CDC/Cdc.v

module CDC #(
    parameter WIDTH = 32,
    parameter STAGES = 3,
    parameter SpiNum = 7



)
(
    input ClkFast_i,
    input [SpiNum-1:0] ClkSlow_i,

    input [WIDTH-1:0] Spi0Ctrl_i,
    input [WIDTH-1:0] Spi0CsCtrl_i,
    input [WIDTH-1:0] Spi0CsDelay_i,
    input [WIDTH-1:0] Spi0TxFifoCtrl_i,
    input [WIDTH-1:0] Spi0RxFifoCtrl_i,

    input [WIDTH-1:0] Spi1Ctrl_i,
    input [WIDTH-1:0] Spi1CsCtrl_i,
    input [WIDTH-1:0] Spi1CsDelay_i,
    input [WIDTH-1:0] Spi1TxFifoCtrl_i,
    input [WIDTH-1:0] Spi1RxFifoCtrl_i,

    input [WIDTH-1:0] Spi2Ctrl_i,
    input [WIDTH-1:0] Spi2CsCtrl_i,
    input [WIDTH-1:0] Spi2CsDelay_i,
    input [WIDTH-1:0] Spi2TxFifoCtrl_i,
    input [WIDTH-1:0] Spi2RxFifoCtrl_i,

    input [WIDTH-1:0] Spi3Ctrl_i,
    input [WIDTH-1:0] Spi3CsCtrl_i,
    input [WIDTH-1:0] Spi3CsDelay_i,
    input [WIDTH-1:0] Spi3TxFifoCtrl_i,
    input [WIDTH-1:0] Spi3RxFifoCtrl_i,

    input [WIDTH-1:0] Spi4Ctrl_i,
    input [WIDTH-1:0] Spi4CsCtrl_i,
    input [WIDTH-1:0] Spi4CsDelay_i,
    input [WIDTH-1:0] Spi4TxFifoCtrl_i,
    input [WIDTH-1:0] Spi4RxFifoCtrl_i,

    input [WIDTH-1:0] Spi5Ctrl_i,
    input [WIDTH-1:0] Spi5CsCtrl_i,
    input [WIDTH-1:0] Spi5CsDelay_i,
    input [WIDTH-1:0] Spi5TxFifoCtrl_i,
    input [WIDTH-1:0] Spi5RxFifoCtrl_i,

    input [WIDTH-1:0] Spi6Ctrl_i,
    input [WIDTH-1:0] Spi6CsCtrl_i,
    input [WIDTH-1:0] Spi6CsDelay_i,
    input [WIDTH-1:0] Spi6TxFifoCtrl_i,
    input [WIDTH-1:0] Spi6RxFifoCtrl_i,

    output [WIDTH-1:0] Spi0Ctrl_o,
    output [WIDTH-1:0] Spi0CsCtrl_o,
    output [WIDTH-1:0] Spi0CsDelay_o,
    output [WIDTH-1:0] Spi0TxFifoCtrl_o,
    output [WIDTH-1:0] Spi0RxFifoCtrl_o,

    output [WIDTH-1:0] Spi1Ctrl_o,
    output [WIDTH-1:0] Spi1CsCtrl_o,
    output [WIDTH-1:0] Spi1CsDelay_o,
    output [WIDTH-1:0] Spi1TxFifoCtrl_o,
    output [WIDTH-1:0] Spi1RxFifoCtrl_o,

    output [WIDTH-1:0] Spi2Ctrl_o,
    output [WIDTH-1:0] Spi2CsCtrl_o,
    output [WIDTH-1:0] Spi2CsDelay_o,
    output [WIDTH-1:0] Spi2TxFifoCtrl_o,
    output [WIDTH-1:0] Spi2RxFifoCtrl_o,

    output [WIDTH-1:0] Spi3Ctrl_o,
    output [WIDTH-1:0] Spi3CsCtrl_o,
    output [WIDTH-1:0] Spi3CsDelay_o,
    output [WIDTH-1:0] Spi3TxFifoCtrl_o,
    output [WIDTH-1:0] Spi3RxFifoCtrl_o,

    output [WIDTH-1:0] Spi4Ctrl_o,
    output [WIDTH-1:0] Spi4CsCtrl_o,
    output [WIDTH-1:0] Spi4CsDelay_o,
    output [WIDTH-1:0] Spi4TxFifoCtrl_o,
    output [WIDTH-1:0] Spi4RxFifoCtrl_o,

    output [WIDTH-1:0] Spi5Ctrl_o,
    output [WIDTH-1:0] Spi5CsCtrl_o,
    output [WIDTH-1:0] Spi5CsDelay_o,
    output [WIDTH-1:0] Spi5TxFifoCtrl_o,
    output [WIDTH-1:0] Spi5RxFifoCtrl_o,
    
    output [WIDTH-1:0] Spi6Ctrl_o,
    output [WIDTH-1:0] Spi6CsCtrl_o,
    output [WIDTH-1:0] Spi6CsDelay_o,
    output [WIDTH-1:0] Spi6TxFifoCtrl_o,
    output [WIDTH-1:0] Spi6RxFifoCtrl_o
    
);

//lauch registers 
reg [WIDTH-1:0] spi0Ctrl;
reg [WIDTH-1:0] spi0CsCtrl;
reg [WIDTH-1:0] spi0CsDelay;
reg [WIDTH-1:0] spi0TxFifoCtrl;
reg [WIDTH-1:0] spi0RxFifoCtrl;

reg [WIDTH-1:0] spi1Ctrl;
reg [WIDTH-1:0] spi1CsCtrl;
reg [WIDTH-1:0] spi1CsDelay;
reg [WIDTH-1:0] spi1TxFifoCtrl;
reg [WIDTH-1:0] spi1RxFifoCtrl;

reg [WIDTH-1:0] spi2Ctrl;
reg [WIDTH-1:0] spi2CsCtrl;
reg [WIDTH-1:0] spi2CsDelay;
reg [WIDTH-1:0] spi2TxFifoCtrl;
reg [WIDTH-1:0] spi2RxFifoCtrl;

reg [WIDTH-1:0] spi3Ctrl;
reg [WIDTH-1:0] spi3CsCtrl;
reg [WIDTH-1:0] spi3CsDelay;
reg [WIDTH-1:0] spi3TxFifoCtrl;
reg [WIDTH-1:0] spi3RxFifoCtrl;

reg [WIDTH-1:0] spi4Ctrl;
reg [WIDTH-1:0] spi4CsCtrl;
reg [WIDTH-1:0] spi4CsDelay;
reg [WIDTH-1:0] spi4TxFifoCtrl;
reg [WIDTH-1:0] spi4RxFifoCtrl;

reg [WIDTH-1:0] spi5Ctrl;
reg [WIDTH-1:0] spi5CsCtrl;
reg [WIDTH-1:0] spi5CsDelay;
reg [WIDTH-1:0] spi5TxFifoCtrl;
reg [WIDTH-1:0] spi5RxFifoCtrl;

reg [WIDTH-1:0] spi6Ctrl;
reg [WIDTH-1:0] spi6CsCtrl;
reg [WIDTH-1:0] spi6CsDelay;
reg [WIDTH-1:0] spi6TxFifoCtrl;
reg [WIDTH-1:0] spi6RxFifoCtrl;

// capture registers
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0Ctrl_c;
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0CsCtrl_c;
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0CsDelay_c;
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0TxFifoCtrl_c;
(* ASYNC_REG = "TRUE" *)reg [STAGES*WIDTH-1:0] spi0RxFifoCtrl_c;

(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1Ctrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1CsCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1CsDelay_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1TxFifoCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi1RxFifoCtrl_c;

(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2Ctrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2CsCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2CsDelay_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2TxFifoCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi2RxFifoCtrl_c;

(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3Ctrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3CsCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3CsDelay_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3TxFifoCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi3RxFifoCtrl_c;

(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4Ctrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4CsCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4CsDelay_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4TxFifoCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi4RxFifoCtrl_c;

(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5Ctrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5CsCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5CsDelay_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5TxFifoCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi5RxFifoCtrl_c;

(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6Ctrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6CsCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6CsDelay_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6TxFifoCtrl_c;
(*ASYNC_REG = "TRUE"*)reg [STAGES*WIDTH-1:0]   spi6RxFifoCtrl_c;

//SPI0
assign Spi0Ctrl_o = spi0Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi0CsDelay_o = spi0CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi0CsCtrl_o = spi0CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi0TxFifoCtrl_o = spi0TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi0RxFifoCtrl_o = spi0RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
//SPI1
assign Spi1Ctrl_o = spi1Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi1CsDelay_o = spi1CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi1CsCtrl_o = spi1CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi1TxFifoCtrl_o = spi1TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi1RxFifoCtrl_o = spi1RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
//SPI2
assign Spi2Ctrl_o = spi2Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi2CsDelay_o = spi2CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi2CsCtrl_o = spi2CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi2TxFifoCtrl_o = spi2TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi2RxFifoCtrl_o = spi2RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
//SPI3
assign Spi3Ctrl_o = spi3Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi3CsDelay_o = spi3CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi3CsCtrl_o = spi3CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi3TxFifoCtrl_o = spi3TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi3RxFifoCtrl_o = spi3RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
//SPI4
assign Spi4Ctrl_o = spi4Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi4CsDelay_o = spi4CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi4CsCtrl_o = spi4CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi4TxFifoCtrl_o = spi4TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi4RxFifoCtrl_o = spi4RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
//SPI5
assign Spi5Ctrl_o = spi5Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi5CsDelay_o = spi5CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi5CsCtrl_o = spi5CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi5TxFifoCtrl_o = spi5TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi5RxFifoCtrl_o = spi5RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
//SPI6
assign Spi6Ctrl_o = spi6Ctrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi6CsDelay_o = spi6CsDelay_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi6CsCtrl_o = spi6CsCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi6TxFifoCtrl_o = spi6TxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
assign Spi6RxFifoCtrl_o = spi6RxFifoCtrl_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];


always @(posedge ClkFast_i) begin
    spi0Ctrl <= Spi0Ctrl_i;
    spi0CsDelay <= Spi0CsDelay_i;
    spi0CsCtrl <= Spi0CsCtrl_i;
    spi0TxFifoCtrl <= Spi0TxFifoCtrl_i;
    spi0RxFifoCtrl <= Spi0RxFifoCtrl_i;
    spi1Ctrl <= Spi1Ctrl_i;
    spi1CsDelay <= Spi1CsDelay_i;
    spi1CsCtrl <= Spi1CsCtrl_i;
    spi1TxFifoCtrl <= Spi1TxFifoCtrl_i;
    spi1RxFifoCtrl <= Spi1RxFifoCtrl_i;
    spi2Ctrl <= Spi2Ctrl_i;
    spi2CsDelay <= Spi2CsDelay_i;
    spi2CsCtrl <= Spi2CsCtrl_i;
    spi2TxFifoCtrl <= Spi2TxFifoCtrl_i;
    spi2RxFifoCtrl <= Spi2RxFifoCtrl_i;
    spi3Ctrl <= Spi3Ctrl_i;
    spi3CsDelay <= Spi3CsDelay_i;
    spi3CsCtrl <= Spi3CsCtrl_i;
    spi3TxFifoCtrl <= Spi3TxFifoCtrl_i;
    spi3RxFifoCtrl <= Spi3RxFifoCtrl_i;
    spi4Ctrl <= Spi4Ctrl_i;
    spi4CsDelay <= Spi4CsDelay_i;
    spi4CsCtrl <= Spi4CsCtrl_i;
    spi4TxFifoCtrl <= Spi4TxFifoCtrl_i;
    spi4RxFifoCtrl <= Spi4RxFifoCtrl_i;
    spi5Ctrl <= Spi5Ctrl_i;
    spi5CsDelay <= Spi5CsDelay_i;
    spi5CsCtrl <= Spi5CsCtrl_i;
    spi5TxFifoCtrl <= Spi5TxFifoCtrl_i;
    spi5RxFifoCtrl <= Spi5RxFifoCtrl_i;
    spi6Ctrl <= Spi6Ctrl_i;
    spi6CsDelay <= Spi6CsDelay_i;
    spi6CsCtrl <= Spi6CsCtrl_i;
    spi6TxFifoCtrl <= Spi6TxFifoCtrl_i;
    spi6RxFifoCtrl <= Spi6RxFifoCtrl_i;
end





always @(posedge ClkSlow_i[0]) begin 
    spi0Ctrl_c <= {spi0Ctrl_c[(STAGES-1)*WIDTH-1:0],spi0Ctrl};
    spi0CsDelay_c <= {spi0CsDelay_c[(STAGES-1)*WIDTH-1:0],spi0CsDelay};
    spi0CsCtrl_c <= {spi0CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi0CsCtrl};
    spi0TxFifoCtrl_c <= {spi0TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi0TxFifoCtrl};
    spi0RxFifoCtrl_c <= {spi0RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi0RxFifoCtrl};
end

always@(posedge ClkSlow_i[1]) begin 
    spi1Ctrl_c <= {spi1Ctrl_c[(STAGES-1)*WIDTH-1:0],spi1Ctrl};
    spi1CsDelay_c <= {spi1CsDelay_c[(STAGES-1)*WIDTH-1:0],spi1CsDelay};
    spi1CsCtrl_c <= {spi1CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi1CsCtrl};
    spi1TxFifoCtrl_c <= {spi1TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi1TxFifoCtrl};
    spi1RxFifoCtrl_c <= {spi1RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi1RxFifoCtrl};
end

always@(posedge ClkSlow_i[2]) begin 
    spi2Ctrl_c <= {spi2Ctrl_c[(STAGES-1)*WIDTH-1:0],spi2Ctrl};
    spi2CsDelay_c <= {spi2CsDelay_c[(STAGES-1)*WIDTH-1:0],spi2CsDelay};
    spi2CsCtrl_c <= {spi2CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi2CsCtrl};
    spi2TxFifoCtrl_c <= {spi2TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi2TxFifoCtrl};
    spi2RxFifoCtrl_c <= {spi2RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi2RxFifoCtrl};
end

always@(posedge ClkSlow_i[3]) begin 
    spi3Ctrl_c <= {spi3Ctrl_c[(STAGES-1)*WIDTH-1:0],spi3Ctrl};
    spi3CsDelay_c <= {spi3CsDelay_c[(STAGES-1)*WIDTH-1:0],spi3CsDelay};
    spi3CsCtrl_c <= {spi3CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi3CsCtrl};
    spi3TxFifoCtrl_c <= {spi3TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi3TxFifoCtrl};
    spi3RxFifoCtrl_c <= {spi3RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi3RxFifoCtrl};
end

always@(posedge ClkSlow_i[4]) begin 
    spi4Ctrl_c <= {spi4Ctrl_c[(STAGES-1)*WIDTH-1:0],spi4Ctrl};
    spi4CsDelay_c <= {spi4CsDelay_c[(STAGES-1)*WIDTH-1:0],spi4CsDelay};
    spi4CsCtrl_c <= {spi4CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi4CsCtrl};
    spi4TxFifoCtrl_c <= {spi4TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi4TxFifoCtrl};
    spi4RxFifoCtrl_c <= {spi4RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi4RxFifoCtrl};
end

always@(posedge ClkSlow_i[5]) begin 
    spi5Ctrl_c <= {spi5Ctrl_c[(STAGES-1)*WIDTH-1:0],spi5Ctrl};
    spi5CsDelay_c <= {spi5CsDelay_c[(STAGES-1)*WIDTH-1:0],spi5CsDelay};
    spi5CsCtrl_c <= {spi5CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi5CsCtrl};
    spi5TxFifoCtrl_c <= {spi5TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi5TxFifoCtrl};
    spi5RxFifoCtrl_c <= {spi5RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi5RxFifoCtrl};
end

always@(posedge ClkSlow_i[6]) begin 
    spi6Ctrl_c <= {spi6Ctrl_c[(STAGES-1)*WIDTH-1:0],spi6Ctrl};
    spi6CsDelay_c <= {spi6CsDelay_c[(STAGES-1)*WIDTH-1:0],spi6CsDelay};
    spi6CsCtrl_c <= {spi6CsCtrl_c[(STAGES-1)*WIDTH-1:0],spi6CsCtrl};
    spi6TxFifoCtrl_c <= {spi6TxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi6TxFifoCtrl};
    spi6RxFifoCtrl_c <= {spi6RxFifoCtrl_c[(STAGES-1)*WIDTH-1:0],spi6RxFifoCtrl};
end





endmodule