S5443_V3/sources_1/new/DataFifo/RxFifoPtrSync.v

module RxFifoPtrSync #(
    parameter WIDTH = 8,
    parameter STAGES = 3



)
(
    input ClkFast_i,
    input ClkSlow_i,
    input [WIDTH-1:0] RxFifoWrPtr_i,

    output [WIDTH-1:0] RxFifoWrPtr_o
);




//lauch registers 
reg [WIDTH-1:0] rxFifoWrPtrReg;


// capture registers
(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoWrPtrReg_c;



assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];


always @(posedge ClkFast_i) begin
    rxFifoWrPtrReg <= RxFifoWrPtr_i;
end





always @(posedge ClkSlow_i) begin
    rxFifoWrPtrReg_c <= {rxFifoWrPtrReg_c[(STAGES-1)*WIDTH-1:0], rxFifoWrPtrReg};
end





endmodule