S5443_V3/sources_1/new/DataFifo/RxFifoRstSync.v

module RxFifoRstSync #(
    parameter WIDTH = 1,
    parameter STAGES = 3



)
(
    input ClkFast_i,
    input ClkSlow_i,
    input [WIDTH-1:0] RxFifoRst_i,

    output [WIDTH-1:0] RxFifoRst_o
);





//lauch registers 
reg [WIDTH-1:0] rxFifoRstReg;


// capture registers
(* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] rxFifoRstReg_c;


assign RxFifoWrPtr_o = rxFifoWrPtrReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];



always @(posedge ClkFast_i) begin
    rxFifoRstReg <= RxFifoRst_i;
end


always @(posedge ClkSlow_i) begin
    rxFifoRstReg_c <= {rxFifoRstReg_c[(STAGES-1)*WIDTH-1:0], rxFifoRstReg};
end





endmodule